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vlsi_hw3 - lowering the output voltage 3 Discuss how...

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Ajay Joshi Hw-3 1. 1. Assume a wafer size of 16inches, a die size of 3.4cm2, 1.5defects/cm2, and α=3. Determine the die yield of this CMOS process run Die yield = Wafer Yield x (1 + (Defects per unit area x Die Area)/a)-a =16 * (1 + ( 1.5 * 3.4 )/3) )^-3 = 0.81 2. A constant input voltage V volts is applied as input Vin of the following circuits, describe how Vout will vary with respect to the time The figure is low pass RC filter. The relationship between input and output voltage calculated taking into account the impedances is known as transfer function. This transfer function is always a function of frequency and is denoted as H(ω). For the low pass filter H(ω)) is H(w) =1/(1 + jwRC) As we know that a capacitors reactance changes with frequency, and its reactance decreases with increasing frequency. Low pass filter is similar to voltage divider when we replace one of the voltage divider resistors with a capacitor. As frequency increases the capacitor impedance drops and more voltage is dropped across R and less across C thus
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Unformatted text preview: lowering the output voltage. 3. Discuss how average power dissipation is calculated for CMOS circuit There are two types of power dissipation in a logic gate: static and dynamic. Static power refers to the power that the gate dissipates in the absence of switching action. On the other hand, dynamic power occurs only when the gate is switched. Here are the following ways to calculate the power dissipation for the CMOS circuit: Dynamic power: the dynamic power dissipation in the CMOS inverter can be calculated by the following equation: Pd = f*C *(Vdd)^2 Where f is the frequency at which the gate is switched, C is the capacitance, and Vdd is the voltage. Static power: it is the power dissipation for DC supply, which can be calculated by: P= IV Where P is a power, I is current, and V is the voltage of the system. 4. Using LTspice simulate the “inverter” logic gate circuit discussed in the class for functional verification. Use 50nm CMOS technology and sizes typically used...
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