Unformatted text preview: lowering the output voltage. 3. Discuss how average power dissipation is calculated for CMOS circuit There are two types of power dissipation in a logic gate: static and dynamic. Static power refers to the power that the gate dissipates in the absence of switching action. On the other hand, dynamic power occurs only when the gate is switched. Here are the following ways to calculate the power dissipation for the CMOS circuit: Dynamic power: the dynamic power dissipation in the CMOS inverter can be calculated by the following equation: Pd = f*C *(Vdd)^2 Where f is the frequency at which the gate is switched, C is the capacitance, and Vdd is the voltage. Static power: it is the power dissipation for DC supply, which can be calculated by: P= IV Where P is a power, I is current, and V is the voltage of the system. 4. Using LTspice simulate the “inverter” logic gate circuit discussed in the class for functional verification. Use 50nm CMOS technology and sizes typically used...
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 Spring '12
 UNT
 Logic gate, Lowpass filter, Electrical impedance, power dissipation

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