Lec04-memory - CSCI 504 Computer Organization Lecture 4...

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1 CSCI 504 Computer Organization Lecture 4 Caches and Memory Systems Dr. Yuan-Shun Dai Computer Science 504 Fall 2004 Adapted from D.A. Patterson, Copyright 2003 UCB
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2 Review: Reducing Misses Classifying Misses: 3 Cs Compulsory —Misses in even an Infinite Cache Capacity —Misses in Fully Associative Size X Cache Conflict —Misses in N-way Associative, Size X Cache More recent, 4th “C”: Coherence - Misses caused by cache coherence .
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3 Review: Miss Rate Reduction 3 Cs: Compulsory, Capacity, Conflict 1. Reduce Misses via Larger Block Size 2. Reduce Misses via Higher Associativity 3. Reducing Misses via Victim Cache 4. Reducing Misses via Pseudo-Associativity 5. Reducing Misses by HW Prefetching Instr, Data 6. Reducing Misses by SW Prefetching Data 7. Reducing Misses by Compiler Optimizations y MissPenalt MissRate HitTime AMAT × + =
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4 Improving Cache Performance Continued 1. Reduce the miss rate, 2. Reduce the miss penalty, or 3. Reduce the time to hit in the cache. y MissPenalt MissRate HitTime AMAT × + =
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5 Write Policy: Write-Through vs Write-Back Write-through: all writes update cache and underlying memory/cache Can always discard cached data - most up-to-date data is in memory Cache control bit: only a valid bit Write-back: all writes simply update cache Can’t just discard cached data - may have to write it back to memory Cache control bits: both valid and dirty bits Other Advantages: Write-through: • memory (or other processors) always have latest data Simpler management of cache Write-back: much lower bandwidth, since data often overwritten multiple times
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6 1. Reducing Miss Penalty: Read Priority over Write on Miss write buffe r CPU in out DRAM (or lower mem) Write Buffer
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7 1. Reducing Miss Penalty: Read Priority over Write on Miss Write-through with write buffers offer RAW conflicts with main memory reads on cache misses If simply wait for write buffer to empty, might increase read miss penalty Check write buffer contents before read; if no conflicts, let the memory access continue Write-back also want buffer to hold misplaced blocks Read miss replacing dirty block Normal: Write dirty block to memory, and then do the read Instead copy the dirty block to a write buffer, then do the read, and then do the write CPU stall less since restarts as soon as do read
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8 2. Reduce Miss Penalty: Early Restart and Critical Word First Don’t wait for full block to be loaded before restarting CPU Early restart —As soon as the requested word of the block arrives, send it to the CPU and let the CPU continue execution Critical Word First —Request the missed word first from memory and send it to the CPU as soon as it arrives; let the CPU continue execution while filling the rest of the words in the block. Also called wrapped fetch and requested word first Generally useful only in large blocks, Spatial locality a problem; tend to want next sequential word, so not clear if benefit by early restart block
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9 3. Reduce Miss Penalty: Non-blocking
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This note was uploaded on 02/28/2012 for the course CSCE 3510 taught by Professor Unt during the Spring '12 term at North Texas.

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Lec04-memory - CSCI 504 Computer Organization Lecture 4...

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