l6-cost - CEG3420 Computer Design Lecture 6: Cost and...

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ceg3420 L6 Cost.1 Fa 1998 UCB CEG3420 Computer Design Lecture 6: Cost and Design Process
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ceg3420 L6 Cost.2 Fa 1998 UCB Administrative Matters ° Review complete ° Read Chapter 4: ALU, Multiply, Divide, FP Mult ° Load balance of discussion sections
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ceg3420 L6 Cost.3 Fa 1998 UCB Year Performance 0.1 1 10 100 1000 1965 1970 1975 1980 1985 1990 1995 2000 Microprocessors Minicomputers Mainframes Supercomputers Review: Performance and Technology Trends ° Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year Feature Size: shrinks 10% / yr. => Switching speed improves 1.2 / yr. Density: improves 1.2x / yr. Die Area: 1.2x / yr. ° RISC lesson is to keep the ISA as simple as possible: Shorter design cycle => fully exploit the advancing technology (~3yr) Advanced branch prediction and pipeline techniques Bigger and more sophisticated on-chip caches
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ceg3420 L6 Cost.4 Fa 1998 UCB Review: Technology, Logic Design and Delay ° CMOSTechnology Trends Complementary: PMOS and NMOS transitors CMOS inverter and CMOS logic gates ° Delay Modeling and Gate Characterization Delay = Internal Delay + (Load Dependent Delay x Output Load) ° Clocking Methodology and Timing Considerations Simplest clocking methodology - All storage elements use the SAME clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time
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ceg3420 L6 Cost.5 Fa 1998 UCB Overview: Cost and Design Process ° Cost and Price ° Design process
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ceg3420 L6 Cost.6 Fa 1998 UCB Integrated Circuit Costs Die cost = Wafer cost Dies per Wafer * Die yield Dies per wafer = π * ( Wafer_diam / 2) 2 π * Wafer_diam Test dies - Wafer Area Die Area 2 * Die Area Die Area Die Yield = Wafer yield α is very dependent on process { 1+ α } Defects_per_unit_area * Die_Area α
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ceg3420 L6 Cost.7 Fa 1998 UCB Die Yield Raw Die Per Wafer wafer diameter die area (mm 2 ) 100 144 196 256 324 400 6”/15cm 139 90 62 44 32 23 8”/20cm 265 177 124 90 68 52 10”/25cm 431 290 206 153 116 90 die yield (???) 23% 19% 16% 12% 11% 10% typical CMOS process: α =2, wafer yield=90%, defect density=2/cm2, 4 test sites/wafer Good Die Per Wafer 6”/15cm 31 16 9 5 3 2 8”/20cm 59 32 19 11 7 5 10”/25cm 96 53 32 20 13 9 typical cost of an 8”, 4 metal layers, 0.5um CMOS wafer: ~$2000
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ceg3420 L6 Cost.8 Fa 1998 UCB Guesses on what the cost is…. Chip Metal Line Wafer Defect Area Dies/ Yield Die Cost layers width cost /cm 2 mm 2 wafer 386DX 2 0.90 $900 1.0 43 360 71% $4 486DX2 3 0.80 $1200 1.0 81 181 54% $12 PowerPC 601 4 0.80 $1700 1.3 121 115 28% $53 HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149 SuperSPARC 3 0.70 $1700 1.6 256 48 13% $272 Pentium 3 0.80 $1500 1.5 296 40 9% $417 From "Estimating IC Manufacturing Costs,” by Linley Gwennap, Microprocessor Report , August 2, 1993, p. 15 What’s wrong with this table???
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ceg3420 L6 Cost.9 Fa 1998 UCB IC cost
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l6-cost - CEG3420 Computer Design Lecture 6: Cost and...

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