Lecture10-1 - CSCE 2610 The Processor: Pipelining MIPS in...

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CSCE 2610 The Processor: Pipelining
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MIPS in the Pipeline As mentioned last time, MIPS separates execution into five stages: IF: Instruction fetch (from memory) ID: Instruction decode (and register access) EX: Execute instruction (calculate address) MEM: Access memory WB: Write result back into register
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Keeping internal data around Four new register arrays are used to store internal data during execution: IF/ID, ID/EX, EX/MEM, and MEM/WB They store to data and control signals for all instructions currently in the pipeline.
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Keeping control signals around Control signals are kept in the new registers, too. They are organized according to which stage they are used in. EX: ALUSrc, ALUOp, RegDst MEM: MemWrite, MemRead, PCSrc WB: MemToReg, RegWrite
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Big Picture (Still Simplified)
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Example Path – lw (IF) Read current instruction (lw). Update program counter to fetch next instruction.
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Example Path – lw (ID) Load base address from register. Extend the offset
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Example Path – lw (EX) Select the immediate as input to ALU Calculate the address in memory
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Example Path – lw (MEM) Read data from memory
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Example Path – lw (WB) Write the memory data to a register. Oops! The write register is no longer valid.
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Writeback Fixed The write-register field needs to be passed through each stage. It is calculated 3 stages before it is used.
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Pipelining Notation Two ways the book uses to show the execution of a pipeline: Resource Usage Form Traditional Box Form
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Traditional Notation
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Resource Notation
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Hazards Pipelining is pretty straightforward when there are no problems. Here are the problems: Data Hazards Control Hazards Structural Hazards Sometimes the pipeline cannot move on intelligently until something is finished.
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Structural Hazards The hardware cannot support the combination of instructions that need to be executed at the same time. Examples: Single memory systems (instruction and data together) Accessing a non-pipelined floating point CPU MIPS is designed to avoid these issues (especially the reduced set we're working with).
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Data Hazards A data hazard occurs when a change in the data is not propagated quickly enough. Example:
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This note was uploaded on 02/28/2012 for the course CSCE 3510 taught by Professor Unt during the Spring '12 term at North Texas.

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Lecture10-1 - CSCE 2610 The Processor: Pipelining MIPS in...

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