final-review - Same as Homework #5 Find the Average Memory...

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CSCE 2610 Final Review
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Parts of the final Total (110%) Short Answers (40%) – more later 4% each 16 questions, in 3 groups Answer 10 of them. Instruction Execution Analysis (20%) 4 questions, 5% each You're given an instruction, what control signals are affected, how does data flow?
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Example: addi $t0, $t1, 10
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Parts of the final Code Analysis – Hazards (15%) 3 snippets, 5% each Detect data/control hazards Stalls/Forwarding Example: lw $s0, 0($sp)# Data hazard (2 stalls before forwarding) beq $s0, $zero, far_away # Control hazard addi $sp, $sp, 4
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Parts of the final Branch Prediction (10%) Same as Homework #4 1-bit and 2-bit modes Example here in class! Cache Behavior (10%) Same as Homework #5 Given a sequence of block addresses, show how the cache will be filled, what will be replaced, and what the hits/misses are. Example here in class!
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Parts of the final Cache Performance (15%) 3 systems, 5% each
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Unformatted text preview: Same as Homework #5 Find the Average Memory Access Time (AMAT) given some cache parameters. Example here in class! Short Answers Chapter 4 Multiplexors What are they for? Arithmetic Logic Unit (ALU) How does it work? Opcodes and the Control Unit Pipelined vs Single-Cycle CPUs Hazards Data, Control, Structural Load-Use Hazard Hazard Detection Short Answers Chapter 5 Compare SRAM and DRAM Locality Spacial, Temporal What is stored in a cache? Write-through and Write-back policies Advantages of Multi-Level Caches Purpose of Virtual Memory Translation-Lookaside Buffer (TLB) Page Fault Short Answers Chapter 6/7 Disk Components Cylinder, Track, Platter, Sector Memory-Mapped I/O OS and Memory Protection Clusters and Cloud Computing Amdahl's Law and Parallelism...
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This note was uploaded on 02/28/2012 for the course CSCE 3510 taught by Professor Unt during the Spring '12 term at North Texas.

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final-review - Same as Homework #5 Find the Average Memory...

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