550-midterm-review-winter2009

550-midterm-review-winter2009 - EECC550 - Shaaban EECC550 -...

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Unformatted text preview: EECC550 - Shaaban EECC550 - Shaaban #1 Midterm Review Winter 2009 1-19-2010 Midterm Questions Overview Four questions from the following: Performance Evaluation: Given MIPS code, estimate performance on a given CPU. Compare performance of different CPU/compiler changes for a given program. May involve computing execution time, speedup, CPI, MIPS rating, etc. Single or multiple enhancement Amdahls Law given parameters before or after the enhancements are applied. Adding support for a new instruction to the textbook versions of: Single cycle MIPS CPU Multi cycle MIPS CPU Dependant RTN for the new instruction and changes to datapath/control. EECC550 - Shaaban EECC550 - Shaaban #2 Midterm Review Winter 2009 1-19-2010 CPU Organization (Design) CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic Units, ...) Ways in which these components are interconnected (buses connections, multiplexors, etc.). How information flows between components. Control Unit Design: Logic and means by which such information flow is controlled. Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram). Hardware description with a suitable language, possibly using Register Transfer Notation (RTN). Components & their connections needed by ISA instructions Control/sequencing of operations of datapath components to realize ISA instructions Components Connections ISA = Instruction Set Architecture The ISA forms an abstraction layer that sets the requirements for both complier and CPU designers EECC550 - Shaaban EECC550 - Shaaban #3 Midterm Review Winter 2009 1-19-2010 Chapter 2 (both editions) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. Motivated by simplifying the ISA and its requirements to: Reduce CPU design complexity Improve CPU performance. CPU Performance Goal: Reduced number of cycles needed per instruction. At least one instruction completed per clock cycle. Simplified addressing modes supported. Usually limited to immediate, register indirect, register displacement, indexed. Load-Store GPR: Only load and store instructions access memory. (Thus more instructions are usually executed than CISC) Fixed-length instruction encoding. (Designed with CPU instruction pipelining in mind). Support of delayed branches....
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This note was uploaded on 02/28/2012 for the course CSCE 3510 taught by Professor Unt during the Spring '12 term at North Texas.

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550-midterm-review-winter2009 - EECC550 - Shaaban EECC550 -...

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