Lecture 4 8405 (2)

Lecture 4 8405 (2) - ECE8405 Class Notes CHAPTER 5 CPU...

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ECE8405 Class Notes CHAPTER 5 - CPU IMPLEMENTATION The CPU consists of the datapath , control, cache , and I/O peripherals and interfaces . This week, we will consider the first two, which form the backbone of the CPU. Today we will consider a non-pipelined implementation of the datapath. R-FORMAT : op(6) rs(5) rt(5) rd(5) shift(5) arith_op(6). Let’s do it from the perspective of the instruction types. Starting with a register-type instruction, what elements do we need in our datapath? rs data(rs) rt Registers ALU data(rt) rd result(rd) IR regWrite ALU_op Instruction Register (IR) stores the instruction currently being executed. The operation can be almost completely combinatorial- updating the IR starts executing the instruction, the addresses flow to the register, data to the ALU, the ALU’s result flows back to the registers and is written. Only problem- if dest_write_enable is enabled before the address of the destination has settled, can spuriously write a wrong location. Usually this is taken care of by enabling the write only during the later half of the clock cycle during which the operation is executed. Where does the instruction come from? Need circuitry to update addresses and read instruction (see next page). The driving force here is the clock, which allows the PC to update, which causes the next instruction to be read and placed into the IR. We can assume for now that the clock period is long enough to fetch the instruction AND execute it! 1
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ADDER PC Program IR Memory 4 Clock Missing is the control circuitry, which decodes the op bits (IR26-IR31) and combined with the low ALUop bits (IR0-IR5), derives control bits for the ALU and registers. Note that shift bits shuffled to ALU also, in case op is a shift. I-FORMAT: I-Format instructions require us to make quite a few changes. First, note that each I-format instruction type (immediate, load/store, and branch) requires different hardware features. Let’s treat them separately. Immediate (op6, rs5, rd5, immed16) To treat an immediate arithmetic operation, we have two problems: 1) The destination reg address rd is in different bits from R-format 2) The ALU needs to operate on the immediate data from the IR To solve the first, we need to use a mux to select whether rd comes from bits 11-15 or 16-20 of the IR. In any case, 11-15 can go to rt, because a read can be done whether or not the data is used! To solve the second, another mux can be used on the lower ALU data input to select whether the data source is the register read rt or the instruction. If the data is in the instruction, a sign extension operation is required (copy MS bit) to make the data 32 bit with the correct sign. 2
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m m X x regDst regWrite ALUsrc bits 0-15 sign extend LOAD/STORE To perform load/store, a few more blocks need to be added. The ALU is used to perform address calculations, using exactly the circuit above. The only difference is that data memory must be included in our system. Thus, we need another mux to select whether the data returned to the register is
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Lecture 4 8405 (2) - ECE8405 Class Notes CHAPTER 5 CPU...

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