ics233project_081 (1)

ics233project_081 (1) - KING FAHD UNIVERSITY OF PETROLEUM...

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Course Project -Term 081 Pipelined Processor Design Due date: Friday, Jan. 30, 2009 Project Objectives: Designing a Pipelined 16-bit MIPS-like processor Using Logisim simulator to model and test the processor Teamwork practice Instruction Set Architecture In this project, you will design a simple 16-bit MIPS-like processor with seven 16-bit general-purpose registers: R1 through R7. R0 is hardwired to zero and cannot be written. There is also one special-purpose 12-bit register, which is the program counter (PC). All instructions are 16 bits and there are three instruction formats: R-type, I-type, and J-type as shown below: R-type format 4-bit opcode (Op), 3-bit register numbers (Rs, Rt, and Rd), and 3-bit function field (funct) I-type format 4-bit opcode (Op), 3-bit register numbers (Rs and Rt), and 6-bit immediate constant J-type format 4-bit opcode (Op) and 12-bit immediate constant For R-type instructions, Rs and Rt specify the two source register numbers, and Rd specifies the destination register number. The function field can specify at most eight functions for a given opcode. Opcodes 0000 and 1111 are reserved for R-type instructions. For I-type instructions, Rs specifies a source register number, and Rt can be a second source or a destination register number. The immediate constant is only 6 bits because of the fixed- size nature of the instruction. The 6-bit immediate constant is assumed to be sign-extended for all instructions. Page 1 of 6 funct 3 Op 4 Rs 3 Rt 3 Rd 3 Immediate 6 Op 4 Rs 3 Rt 3 Immediate 12 Op 4
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For J-type, a 12-bit immediate constant is used for J (jump), JAL (jump-and-link), and LUI (load upper immediate) instructions. Instruction Encoding Sixteen R-type instructions, eleven I-type instructions, and three J-type instructions are defined. These instructions, their meaning, and their encoding are shown below: Instr Meaning Encoding ADD Reg(Rd) = Reg(Rs) + Reg(Rt) Op = 0000 Rs Rt Rd f = 000 SUB Reg(Rd) = Reg(Rs) – Reg(Rt) Op = 0000 Rs Rt Rd f = 001 SLT Reg(Rd) = Reg(Rs) signed< Reg(Rt) Op = 0000 Rs Rt Rd f = 010 SLTU Reg(Rd) = Reg(Rs) unsigned< Reg(Rt) Op = 0000 Rs Rt Rd f = 011 AND Op = 0000 Rs Rt Rd f = 100 OR Reg(Rd) = Reg(Rs) | Reg(Rt) Op = 0000 Rs Rt Rd f = 101 NOR Reg(Rd) = ~(Reg(Rs) | Reg(Rt)) Op = 0000 Rs Rt Rd f = 110 XOR Reg(Rd) = Reg(Rs) ^ Reg(Rt) Op = 0000 Rs Rt Rd f = 111 SLL Reg(Rd) = Reg(Rs) << Reg(Rt) Op = 1111 Rs Rt Rd f = 000 SRL Reg(Rd) = Reg(Rs) zero>> Reg(Rt) Op = 1111 Rs Rt Rd f = 001 SRA Reg(Rd) = Reg(Rs) sign>> Reg(Rt) Op = 1111 Rs Rt Rd f = 010 ROL Reg(Rd) = Reg(Rs) rotate<< Reg(Rt) Op = 1111 Rs Rt Rd f = 011
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ics233project_081 (1) - KING FAHD UNIVERSITY OF PETROLEUM...

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