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? ? ? ? clk ? ? ? ? rst PC PC_in[31:0] PC [31:0](to add1 and I-mem) IF/ID in PC4 [31:0] ins [31:0] out: PC4_ifid[31:0] ins_ifid [31:0], rd_idex[4:0], rt_idex[4:0], rs_regs[4:0], rt_regs[4:0], immed_ifid[15:0] inside: shift2[31:0] PC_Branch[31:0] ID/EX In: WB_ifid[1:0](reg_write:mento_reg) M_ifid[2:0](Branch:Men_read:Men_write) EX_ifid[3:0] (RegDst, ALUOp[1:0], ALUSrc) Out: WB_idex[1:0] M_idex[2:0] RegDst ALUOp[1:0] ALUSrc PC4_idex[31:0] rs_idex[31:0]
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rt_idex[31:0] immed_idex[31:0] rdw[4:0] rtw[4:0] inside EX: ALUin1[31:0] ALUin2[31:0] ALUcontrol[3:0]
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Unformatted text preview: Muxfb[31:0] EX/MEM In: ALU_result[31:0] write_regidex[4:0] out: WB_mem[1:0](reg_write:mento_reg) Branch Mem_read Mem_write PC_shift[31:0] ALUr_mem[31:0] rt_mem[31:0] write_regmem[4:0] inside: BDst MEN/WB In: read_data[31:0] out: reg_write datawreg ALUr [31:0] data_men[31:0] write_regs[4:0] inside: write_data[31:0] Forward: In: rs_f[4:0] rt_f[4:0] out: FA[1:0] FB[1:0] Hazard: Out: PCwrite Ifidwrite Controlwrite ? ? ? ? : 1. ? ? ? ? pipeline ? ? ? ,...
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