TLBTags - Dealing With TLB Tags or I Want to Build a...

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Dealing With TLB Tags or I Want to Build a System, What Can L4 Do for Me? Gernot Heiser School of Computer Science and Engineering University of NSW, Sydney 2052, Australia [email protected] October 11, 2001 Abstract This paper discusses TLB tags found on various archi- tectures, their use in single- and multi-address-space op- erating systems, and the implications on the L4 API. 1 Introduction Most modern computer architectures tag entries in the translation lookaside buffer (TLB) with one or more fields which identify the addressing or protection con- text to which an entry belongs. This makes it possible to minimise TLB flushes during context switches. This paper presents the tagging scheme used by vari- ous architectures. It first presents the schemes presently in use. It then examines each scheme from the angle of how it might be used in the context of a single-address- space operating system (SASOS), as well as a more traditional multi-address-space operating system (MA- SOS). Finally it attempts to draw conclusions on which L4 mechanisms might be appropriate to support the use of the various schemes for the implementation of both kinds of operating systems. APIs for dealing with tags are suggested. 2 TLB Tags The following tagging schemes are in used in contem- porary architectures: Address-space identifier (ASID): Each TLB entry (TLBE) is tagged with an ID representing the process it belongs to. On address translation the contents of an ASID register is combined with the page number to form the key for which the TLB is searched. TLB entries are thus only considered valid for translation if they match the value of an ASID register, which is part of the executing pro- cess’s context. 1 The total number of possible ASID values is typically of the order 2 8 2 12 . ASIDs are used on the MIPS [ Hei93 ], Alpha [ Dig92 ] and UltraSPARC [ Sun97 ] architectures, as well as some PowerPC processors [ IBM01 ]. The Pentium’s segment registers can, in certain cir- cumstances, be used like ASIDs (Liedtke’s small- address-space trick [ Lie95 ]), although they are conceptually more akin to region IDs. Region identifier (RID): This represents a generalisa- tion of the ASID scheme. Each TLB entry is tagged by a RID, and several RIDs may be active at any time. This makes it easier to share data (and makes a global bit unnecessary). RIDs are deter- mined by the leading three bits of the virtual ad- dress, the virtual region number (VRN). The VRN identifies one of 8 region registers (RRs), which contain the RID corresponding to the virtual ad- dress. RIDs are 24 bits wide, but the full size may not be supported by the hardware. However, the ar- chitecture specifies that at least 2 18 RIDs are sup- ported on IA-64. RIDs are used on HP PA-RISC [ Lee89 ] (called space IDs there) and IA-64 [ Int00 ]. Protection key (PK):
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This note was uploaded on 03/01/2012 for the course CMP 426 taught by Professor Gwangs.jung during the Spring '12 term at CUNY Lehman.

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TLBTags - Dealing With TLB Tags or I Want to Build a...

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