chapter2-device02 - Digital IC 2: Device Introduction CMOS...

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Unformatted text preview: Digital IC 2: Device Introduction CMOS VLSI Design 2.CMOS Transistor Theory Fu yuzhuo School of microelectronics,SJTU Digital IC 2: Device outline • PN junction principle • CMOS transistor introduction • Ideal I-V characteristics under static conditions • Velocity Saturation • Dynamic Characteristics • Nonideal I-V effects 2/42 Digital IC 2: Device Capacitance • Any two conductors separated by an insulator have capacitance • Gate to channel capacitor is very important • Creates channel charge necessary for operation • Source and drain have capacitance to body • Across reverse-biased diodes • Called diffusion capacitance because it is associated with source/drain diffusion 3/42 Digital IC 2: Device Diffusion Capacitance • C sb , C db • Undesirable, called parasitic capacitance • Capacitance depends on area and perimeter • Use small diffusion nodes • Comparable to C g for contacted diff • ½ C g for uncontacted • Varies with process 4/42 Digital IC 2: Device Capacitance components • MOS structure capacitances • Overlap cap. • Channel capacitances • Gate-body cap. • Gate-source cap. • Gate-drain cap. • Junction/diffusion capacitances • Bottom-plate cap. • Side-well cap. D S G B C GD C GS C SB C DB C GB 2011/3/16 5 Digital IC 2: Device The Gate Capacitance W C W x C C C o d ox GDO GSO t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain n + W 6/42 Digital IC 2: Device Gate channel Capacitance S D G C GC S D G C GC S D G C GC Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off 7/42 Digital IC 2: Device Gate Capacitance 8 WLC ox WLC ox 2 2WLC o x 3 C GC C GCS V DS / ( V GS-V T ) C GCD 1 C GC C GCS = C GCD C GC B WLC ox WLC ox 2 V GS Capacitance as a function of V GS (with V DS = 0) Capacitance as a function of the degree of saturation Digital IC 2: Device C-V curves 9 Digital IC 2: Device Measuring the Gate Cap 2 1.52 1 2 0.5 0 3 4 5 6 7 8 9 10 3 10 2 16 2 V GS (V) V GS Gate Capacitance (F) 0.5 1 1.5 2 2 2 I dt dV I V C dt dV V C I GS GS G GS GS G ) ( ) ( 10 Digital IC 2: Device Diffusion Area Capacitance Bottom Side wall Side wall Channel Source N D Channel-stop implant N A 1 Substrate N A W x j D S 11/42 ) 2 ( W L C C PERIMETER C AREA C C C C S jsw jLSW jsw j sw bottom diff Digital IC 2: Device An example of Diffusion Capacitance • C gc =WLC ox =0.24*0.36*5.7=0.49fF • C overlap =2*C o *W=2*0.3*0.36=0.216fF • C diff-s =WD s *C j +(W+2D s )C jsw = 0.36*0.625*2+(0.36+0.625*2)*0.275=0.44fF NMOS:t ox =6nm,L=0.24um,W=0.36um,L D =L S =0.625um,C O =3X10-10 F/m,C j0 =2X10-3 F/m...
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chapter2-device02 - Digital IC 2: Device Introduction CMOS...

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