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Unformatted text preview: hapter2- omework Chapter2 homework or the circuit in Figure 0 2 s 3 3 V Assume • 2-1 For the circuit in Figure 0.2, Vs = 3.3 V. Assume AD = 12 μ m 2 , φ = 0.65 V, and m = 0.5. N A = 2.5 E16 nd = 5 E15. and N D 5 E15. • a. Find I D and V D . • the diode forward- r reverse- iased? b. Is the diode forward or reverse biased? • c. Find the depletion region width, Wj , of the diode. • se the parallel late model to find the junction d. Use the parallel-plate model to find the junction capacitance, Cj . • . et s = 1.5 V. Again using the parallel- late e. Set Vs 1.5 V. Again using the parallel plate model, explain qualitatively why Cj increases. Digital IC 2: Device Slide 1 omework homework Determine the NMOS and PMOS mode of operation • 2-2 Determine the NMOS and PMOS mode of operation (saturation, linear, or cutoff) and drain current ID for each of the biasing configurations given below. Verify with SPICE. Use the following transistor data: NMOS: k' n = 115 μ A/V 2 , V T0 = 0.43 V, = 0....
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- Spring '10
- Transistor, P-n junction, VDS