chapter3-inverter02 - Digital Integrated Circuits YuZhuo Fu

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Digital IC Introduction Digital Integrated Circuits YuZhuo Fu contact:fuyuzhuo@ic.sjtu.edu.cn Office location 417 room WeiDianZi building,No 800 DongChuan road,MinHang Campus
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Digital IC Introduction 3.CMOS Inverter
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Digital IC 3 outline CMOS at a glance CMOS static behavior CMOS dynamic behavior Power, Energy, and Energy Delay Perspective tech.
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Digital IC 4 CMOS dynamic characteristic CMOS capacitances mosaic CMOS propagation delay Optimizing inverter sizing
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Digital IC 5 Circuit Under Design V DD V V in V out M 1 M 2 M 3 M 4 V out 2 This two-inverter circuit will be manufactured in a twin-well process.
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Digital IC CMOS Inverter: Transient Response 6 V DD V out V in = V DD R on C L t pHL = f(R on .C L ) = 0.69 R C L t V out V DD R on C L 1 0.5 ln(0.5) 0.36
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Digital IC 7 CMOS capacitance mosaic Wire capacitance Junction(diffusion) capacitance Gate capacitance Most of them are nonlinear functions!
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Digital IC 8 Computing the Capacitances V DD V DD V in V out M 1 M 2 M 3 M 4 C db 2 C db 1 C gd 12 C w C g 4 C g 3 V out 2 Fanout Interconnect V out V in C L Simplified Model Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m m =2 l
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Digital IC 9 Capacitance model D S G B C GD C GS C SB C DB C GB Ddiff DB Sdiff SB GCB GB GCD GDO GD GCS GSO GS C C C C C C C C C C C C
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Digital IC 10 The Miller Effect V in M 1 C gd 1 V out D V D V V in M 1 V out D V D V 2 C gd 1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”
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Digital IC Diffusion capacitances Slide 11 0 j eq C K = C ] ) V - Φ ( - ) V - Φ [( m) - )(1 V - (V Φ - = K m - 1 low 0 m - 1 high 0 m 0
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Digital IC Miller effect 12
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Digital IC 13 Computing the Capacitances C ox (fF/um 2 ) C o (fF/um) C j (fF/um 2 ) m j Φ b (V) C jsw (fF/um) M jsw Φ bsw (V) NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9 PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9 CDG0 C J C JSW W/L AD(um 2 ) PD(um) AS(um 2 ) PS(um) NMOS 3/2 19 15 19 15 PMOS 9/2 45 19 45 19
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Digital IC Computing the Capacitances Slide 14 Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m m =2 l AD=4*4+3*1=16+3=19λ 2 PD=1+4+4+4+1+1=15λ
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Digital IC Computing the Capacitances V high =-2.5V,V low =-1.25V[NMOS,{2.5V->1.25V} HL] Bottom plate:K eqn (m=0.5,Φ 0 =0.9)=0.57 Sidewall:K eqwn (m=0.44,Φ 0 =0.9)=0.61 V low =0V,V high =-1.25V [NMOS,{0V->1.25V}LH] Bottom plate:K eqn (m=0.5,Φ 0 =0.9)=0.79 Sidewall:K eqwn (m=0.44,Φ 0 =0.9)=0.81 V high =-1.25V,V low =0V [PMOS,{2.5V->1.25V}HL] Bottom plate:K eqp (m=0.48,Φ 0 =0.9)=0.79 Sidewall:K eqwp (m=0.32,Φ 0 =0.9)=0.86 V high =-2.5V,V low =-1.25V [PMOS,{0V->1.25V}LH] Bottom plate:K eqp (m=0.48,Φ 0 =0.9)=0.59 Sidewall:K eqwp (m=0.32,Φ 0 =0.9)=0.7 15
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Digital IC 16 Computing the Capacitances capacitor expression Value(fF) (H->L) Value(fF) (L->H) C gd1 2CGD0 n *W n 0.23 0.23 C gd2 2CGD0 p *W p 0.61 0.61 C db1 K eqn AD n CJ+K eqwn PD n CJSW 0.66 0.90 C db2 K eqn AD n CJ+K eqwn PD n CJSW 1.5 1.15 C g3 (CGD0 n +CGSO n )W n +C ox W n L n 0.76 0.76 C g4 (CGD0 p +CGSO p )W p +C ox W p L p 2.28 2.28 C w 0.12 0.12 C L 6.1 6.0
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Digital IC Introduction Computing it more simple by estimation
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter3-inverter02 - Digital Integrated Circuits YuZhuo Fu

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