chapter3-inverter03 - Digital Integrated Digital Integrated...

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igital Integrated Digital Integrated ircuits Circuits YuZhuo Fu contact:[email protected] Office location 417 room WeiDianZi building,No 800 DongChuan road,MinHang Campus Digital IC Introduction
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3.CMOS Inverter Digital IC Introduction
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outline CMOS at a glance CMOS static behavior CMOS dynamic behavior Power, Energy, and Energy Delay •P e r s pective tech. Digital IC 3
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Dynamic Power Consumption yp (dis)charge process • CL is charged through pMOS on-resistance • CL is discharged through nMOS on-resistance Power distribution • Charge processing:One part of Supply power is dissipated in the pMOS transistor,another part is dissipated in the charge CL • Discharge processing:all dissipated in the nMOS transistor Digital IC 4
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Precise measure of dynamic power consumption ∫∫ = = dd dd out L dd dd V V dt dt dv C V dt V t i E ) ( = = dd V d ut d V C dv V C 2 0 0 dd L out dd L 0 ∞∞ ut dv = = d dd out out L out V C dt v dt C dt v t i E 00 ) ( = = dd V dd L out out L V C dv v C 0 2 2 Digital IC 5
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Output voltages and supply current during is harge of C (dis)charge of C L Energy dissipation is independent of the size Power consumption is dependent of device switching number. charge discharge Digital IC 6
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Power and Energy Figures of Merit gy g Power consumption in Watts • determines battery life in hours Peak power etermines power ground wiring designs determines power ground wiring designs • sets packaging limits •i m pacts signal noise margin and reliability analysis Energy efficiency in Joules • rate at which power is consumed over time Energy = power * delay • Joules = Watts * seconds wer energy number means less power to perform a lower energy number means less power to perform a computation at the same frequency Digital IC
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Power versus Energy ower is height of curve Watts Power is height of curve pproach 1 Lower power design could simply be slower Approach 1 Approach 2 time atts Energy is area under curve Watts Approach 1 Two approaches require the same energy time Approach 2 Digital IC
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PDP and EDP ower elay product (PDP) = (C 2 Power-delay product (PDP) = P av * t p = (C L V DD 2 )/2 • PDP is the average energy consumed per switching vent (Watts * sec = Joule) event (Watts sec = Joule) • lower power design could simply be a slower design nergy elay product (EDP) = PDP * * Energy-delay product (EDP) = PDP tp = P av t p 2 • EDP is the average energy consumed multiplied by e computation time required the computation time required • takes into account that one can trade increased elay for lower energy/operation( .g.,via upply delay for lower energy/operation(e.g.,via supply voltage scaling that increases delay,but decreases energy consumption) Digital IC
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PDP and EDP 15 d malize energy-delay 10 ay (no energy delay 5 gy -De 0 Ene llows one to understand tradeoffs better 0 .
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter3-inverter03 - Digital Integrated Digital Integrated...

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