chapter4-comlogic01 - Digital Integrated Circuits A Design...

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Digital IC Introduction Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU
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Digital IC 2 Combinational vs. Sequential Logic Combinational Sequential Output = f ( In ) Output = f ( In, Previous In ) Combinational Logic Circuit Out In Combinational Logic Circuit Out In State
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Digital IC 3 agenda Static CMOS design Ratioed logic design___Pseudo NMOS Pass transistor design Dynamic logic
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Digital IC 4 Static CMOS logic Static CMOS review Static CMOS layout tricky Static CMOS VTC data dependency CMOS propagate delay definitions RC model Static CMOS size fan-in/fan-out tech. Logic effort CMOS power analysis
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Digital IC 5 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD or V SS via a low-resistive path The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods) This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes
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Digital IC Construction of PDN NMOS devices in series implement a NAND function NMOS devices in parallel implement a NOR function A B A • B A B A + B
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Digital IC Dual PUN and PDN PUN and PDN are dual networks DeMorgan’s theorems • A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B] • A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) Number of transistors for an N-input logic gate is 2N
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Digital IC CMOS NAND A B A • B A B A B F 0 0 1 0 1 1 1 0 1 1 1 0 A B
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Digital IC CMOS NOR A + B A B A B F 0 0 1 0 1 0 1 0 0 1 1 0 A B A B
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Digital IC Complex CMOS Gate OUT = !(D + A • (B + C)) D A B C D A B C
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Digital IC Standard Cell Layout Methodology signals Routing channel V DD GND What logic function is this?
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Digital IC OAI21 Logic Graph C A B X = !(C • (A + B)) B A C i j j V DD X X i GND A B C PUN PDN A B C
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Digital IC Two Stick Layouts of !(C (A + B)) A B C X V DD GND X C A B V DD GND uninterrupted diffusion strip
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Digital IC Consistent Euler Path j V DD X X i GND A B C A B C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once
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Digital IC OAI22 Logic Graph C A B X = !((A+B)•(C+D)) B A D V DD X X GND A B C PUN PDN C D D A B C D
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Digital IC OAI22 Layout B A D V DD GND C X Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)
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Digital IC VTC is Data-Dependent The threshold voltage of M 2 is higher than M 1 due to the body effect ( ) V Tn2 = V Tn0 + (
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter4-comlogic01 - Digital Integrated Circuits A Design...

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