chapter4-comlogic02 - Digital Integrated Circuits A Design...

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Digital IC Introduction Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU
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Digital IC 2 Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis
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Digital IC Sizing Logic Paths for Speed Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain – can we generalize it for any type of logic? 3
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Digital IC ) f ( 0 g p t t p p 4 Modified formula ) f 1 ( ) 1 ( 0 0 p g ext p p t C C t t Electric effort logic effort Intrinsic ratio R par =R inv
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Digital IC Modified formula 5 ) ( ) ( ) ( ) ( . 2 ln ) .( 2 0 0 0 gf p t C C C C C C t C C C C C C t C C C C C C C R R C C t t t p g ext ginv g int par p g ext g p g ext g inv ext ext p
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Digital IC Outline about logic effort Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary 6
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Digital IC Introduction Chip designers face a bewildering array of choices • What is the best circuit topology for a function? • How many stages of logic give least delay? • How wide should the transistors be? Logical effort is a method to make these decisions • Uses a simple model of delay • Allows back-of-the-envelope calculations • Helps make rapid comparisons between alternatives • Emphasizes remarkable symmetries 7
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Digital IC Example Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? 8 A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
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Digital IC 9 Delay in a Logic Gate Express delays in process-independent unit abs d d   3RC 12 ps in 180 nm process 40 ps in 0.6 m m process
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Digital IC Delay in a Logic Gate Express delays in process-independent unit Delay has two components 10 abs d d h p d
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Digital IC Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay h = gf (a.k.a. stage effort) • Again has two components 11 abs d d h p d
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Digital IC Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay h= g f (a.k.a. stage effort) • Again has two components g : logical effort • Measures relative ability of gate to deliver current • g 1 for inverter 12 abs d d h p d
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter4-comlogic02 - Digital Integrated Circuits A Design...

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