chapter4-comlogic03 - Ratioed Logic Introduction Digital IC...

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Ratioed Logic Digital IC Introduction EE141 1
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atioed Logic design Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 2
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Ratioed Logic V DD V DD V DD Resistive epletion MOS F R L Load F F V SS es s ve Depletion Load PMOS Load V T < 0 PDN In 1 In 2 In 3 In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS Digital IC 3
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ow to obtain a good load How to obtain a good load What is a good load • Low power •V OL tend to zero • Charge time short (large charge current) Memory address decoder match the structure • Low power when address hold the line • Change quickly when address content is changed Digital IC 4
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atioed Logic design Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 5
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Ratioed Logic-resistive load D V DD Resistive N transistors + Load R L Load • V OH = V • V L = R N F V OL PN R + R L PDN In 1 In 2 In 3 • Assymetrical response • Static power consumption V SS • t pL = 0.69 R L C L Digital IC 6
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esistive load Resistive load Could not be to low D PDN L R • In order to obtain wide range low noise margin R L >>R PDN DD L PDN OL V R R V + • Then resistive size should be adjust Could not be to high Then enough large current could give quick switch time, because L L pLH C R t 69 . 0 = • Decrease power consumption as soon as possible L PDN L pHL C R R t ) ( 69 . 0 = Digital IC 7
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atioed Logic design Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 8
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Active Loads D D V DD V DD Depletion PMOS V SS Load Load V T < 0 In 1 F DN In 1 F DN In 2 In 3 PDN In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-NMOS Digital IC 9
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epletion NMOS load Depletion NMOS load Depletion load has negative threshold voltage • It is reasonable when we assume the load transistor works at saturate state, just like a current source •P r a c t i c a l l y, the load curve slant down 2 , 2 Tn load n L V k I = • Load transistor’s source is connect with output, which V SB will effect threshold voltage of the transistor Compared with resistive load, depletion load has smaller area • 40k Ω resistive load need 3200 μ m2(0.5um) which could occupy 1000 unit transistor Digital IC 10
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Depletion NMOS ratios computing At leas, V OL should close next stage MOS transistor 3 . 0 dd t out V V V 3 . 0 + × dd load NMOSs PDN PDN dd V R R R V 7 3 load NMOS PDN R R 3 load NMOSs W 7 PDN W Inverter: nMOS Digital IC 11
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atioed Logic design Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 12
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seudo- MOS ratios computing Pseudo NMOS ratios computing
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter4-comlogic03 - Ratioed Logic Introduction Digital IC...

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