chapter4-comlogic04 - Digital Integrated Circuits A Designg...

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Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Digital IC Introduction
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Dynamic Logic Digital IC Introduction EE141 2
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ynamic logic outline Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 3
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A first glance of dynamic logic Basic components • PDN,just like CMOS and pseudo-NMOS p • Clock control transistors seperate circuit to two hases phases Dynamic logic’s two phases • precharge • evaluation Digital IC 4
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ynamic CMOS Dynamic CMOS •I n static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. n- of quires 2 - pe + - pe) devices fan in of n requires 2 n ( n N type n P type) devices •D ynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 ( n +1 N-type + 1 P-type) transistors Digital IC 5
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Dynamic Gate M p Clk ut ut Clk M p In 1 DN Out C L Out A In 2 PDN In 3 lk B C M e Clk Clk M e wo phase operation Two phase operation Precharge (CLK = 0) valuate LK = 1) Digital IC 6 Evaluate (CLK 1)
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Dynamic Gate M p Clk ut ut Clk M p on 1 off In 1 DN Out C L Out A ((AB)+C) In 2 PDN In 3 lk B C M e Clk Clk M e wo phase operation off on Two phase operation Precharge (Clk = 0) valuate(Clk = 1) Digital IC 7 Evaluate(Clk 1)
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onditions on Output Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. puts to the gate can make t most ne transition Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L Digital IC 8
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ynamic Logic Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate 2 AY /3 2/3 Y 1 Y φ 1 4/3 A 1 A tatic Pseudo-nMOS Dynamic Sa c seudo OS ya c φ Precharge Evaluate Precharge Y Digital IC Slide 9
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he Foot The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. Y φ precharge transistor φ Y inputs φ Y inputs A foot f f footed unfooted Digital IC Slide 10
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ogical Effort Logical Effort Inverter NAND2 NOR2 1 φ 1 1 A Y 2 2 B A Y AB 1 1 1 g d = = g d = = g d = = Y φ φ unfooted p d p d p d 1 φ 2 1 A Y 3 3 B A Y 2 2 1 g d = p = g d = = g d = = Y φ φ footed 3 2 2 d d d Digital IC Slide 11
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ogical Effort Logical Effort Inverter NAND2 NOR2 1 1 A Y 2 2 1 B A Y AB 1 1 1 = 1/3 = 2/3 = 1/3 Y φ φ φ unfooted g d 1/3 p d = 2/3 g d 2/3 p d = 3/3 g d 1/3 p d = 3/3 2 1 A Y 3 3 1 B A Y 2 2 1 g d = 2/3 g d = 3/3 g d = 2/3 Y φ φ φ footed p d = 3/3 p d = 4/3 p d = 5/3 3 2 2 Digital IC Slide 12
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onotonicity Monotonicity Dynamic gates require monotonically rising inputs during evaluation •0 - > 0 1 0 -> 1 •1 - > 1 But not 1 -> 0 violates monotonicity during evaluation φ Precharge Evaluate Precharge A Y A φ Output should rise but does not Digital IC Slide 13
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This note was uploaded on 03/01/2012 for the course MR 310 taught by Professor Fuyuzhuo during the Spring '10 term at Shanghai Jiao Tong University.

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chapter4-comlogic04 - Digital Integrated Circuits A Designg...

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