chapter4-comlogicHW

# chapter4-comlogicHW - Digital Integrated Circuits A Design...

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Unformatted text preview: Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Digital IC Introduction omework homework • Sketch a 4-input NAND gate with transistor widths chosen to achieve effective rise and fall resistance equal to a unit inverter. • Compute the rising and falling propagation delays(in terms of R and C) of the NAND gate driving h identical NAND gates using the ELMORE delay model • Compute the rising and falling contamination delays(in terms of R and C) of the NAND gate driving h identical NAND gates sing the ELMORE delay model using the ELMORE delay model • If C=2fF/um and R=2.5kohm.um in a 180nm, what is the delay of a fanout-of-3 NAND gate? Digital IC 2 • Select gate sizes x and y for least delay from A to B Digital IC 3 • Consider four designs of a 6-input AND gate shown in figure. Develop and expression for delay of each path if the path electrical effort is H. what design is fastest of =1? For H=5? For H=20? Explain your conclusion H=1? For H=5? For H=20? Explain your conclusion intuitively Digital IC 4 •...
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chapter4-comlogicHW - Digital Integrated Circuits A Design...

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