chapter6-wire - Digital Integrated Circuits A Design...

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Digital IC Introduction Digital Integrated Circuits A Design Perspective The Wire Thanks for Dr.Guoyong.SHI for his slides contributed for the talk
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Digital IC ± The Wire transmitters receivers schematics physical
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Digital IC ± Interconnect Impact on Chip
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Digital IC ± Wire Models All-inclusive model Capacitance-only
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Digital IC Impact of Interconnect Parasitics Interconnect parasitics • reduce reliability • affect performance and power Classes of parasitics • Capacitive/Resistive/Inductive Interwire capacitance ignored condition • Separation between neighboring wires is large,or wires only run together for a short distance ±
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Digital IC Nature of Interconnect ± 10 100 1,000 10,000 100,000 Length (u) No of nets (Log Scale) Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Local Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel
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Digital IC Introduction INTERCONNECT ±
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Digital IC Capacitance of Wire Interconnect ± V DD V DD V in V out M 1 M 2 M 3 M 4 C db 2 C db 1 C gd 12 C w C g 4 C g 3 V out 2 Fanout Interconnect V out V in C L Simplified Model
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Digital IC Capacitance: The Parallel Plate Model ± Dielectric Substrate L W H t di Electrical-field li Cu rre nt flow WL t c di di int ε = L L Cwire S S S S S 1 = = Too simplistic when W/H ratio become small 0 di ε k = ε k = 3.9 for SiO 2 Processes are starting to use low-k dielectrics k 3 (or less) as dielectrics use air pockets
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Digital IC ±² Permittivity
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Digital IC ±± Fringing Capacitance W - H/2 H + (a) (b) Over the years, a steady reduction in the W/H ratio which has even dropped below 1
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Digital IC ±² Fringing versus Parallel Plate (from [Bakoglu89]) Including fringing cap. Gap
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Digital IC Interwire Capacitance ±² fringing parallel
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Digital IC ±² Impact of Interwire Capacitance (from [Bakoglu89]) Interwire capacitance starts to dominate when W becomes smaller than 1.75H
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