chapter7 - Digital IC Introduction Digital Integrated...

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Unformatted text preview: Digital IC Introduction Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits Digital IC Design Sequential Logic Circuits • Introduction • Timing • Static Latches and Registers • Dynamic Latches and Registers sequentional logic ¡ Digital IC Design Sequential Logic Circuits • Introduction • Timing • Static Latches and Registers • Dynamic Latches and Registers sequentional logic ¡ Digital IC Sequencing • Combinational logic • output depends on current inputs • Sequential logic • output depends on current and previous inputs • Requires separating previous, current, future • Called state or tokens • Ex: FSM, pipeline CL clk in out clk clk clk CL CL Pipeline Finite State Machine ¡ Digital IC Sequencing Cont. • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable • Light pulses (tokens) are sent down cable • Next pulse sent before first reaches end of cable • No need for hardware to separate pulses • But dispersion sets min time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high • Delay fast tokens so they don ’ t catch slow ones. sequentional logic ¡ Digital IC Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay • Called sequencing overhead • Some people call this clocking overhead • But it applies to asynchronous circuits too • Inevitable side effect of maintaining sequence sequentional logic ¡ Digital IC Sequencing Elements • Latch : Level sensitive • a.k.a. transparent latch, D latch • Flip-flop : edge triggered • A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams • Transparent • Opaque • Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop) sequentional logic ¡ Digital IC Sequential Logic 2 storage mechanisms • positive feedback • charge-based COMBINATIONAL LOGIC Registers Outputs Next state CLK Q D Current State Inputs Generic finite- state machine Synchronous,rising edge/positive edge triggered,falling edge/negative edge triggered sequentional logic ¡ /76 Digital IC Naming Conventions • In our text: • a latch is level sensitive • a register is edge-triggered • There are many different naming conventions • For instance, many books call edge-triggered elements flip-flops • This leads to confusion however sequentional logic ¡ Digital IC Latch versus Register Latch stores data when clock is low D Clk Q D Clk Q Register stores data when clock rises Clk Clk D D Q Q sequentional logic ¡ /76 Digital IC Latches sequentional logic ¡¢ /76 Digital IC Latch-Based Design • N latch is transparent when = 0 • P latch is transparent when = 1 N Latch Logic Logic P Latch sequentional logic ¡¡ /76 Digital IC Timing Definitions...
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chapter7 - Digital IC Introduction Digital Integrated...

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