exam2_s08_solution - Last (family) name: _ First (given)...

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ECE/CS 752 Spring 2008 Midterm 2 -- Page 1 Last (family) name: _________________________ First (given) name: _________________________ Student I.D. #: _____________________________ Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 752 Advanced Computer Architecture I Midterm Exam 2 Distributed Friday, May 5, 2008 / Due by 5pmon Monday, May 12, 2008 Please place completed exam in Prof. Lipasti’s mailbox on the first floor of EH4613. Instructions: 1. This exam is open books, open notes, and open all handouts (including previous homeworks and exams, project descriptions, textbook, and readings). However, it must be your own work--do not discuss any aspects of the exam problems with other students until after all exams have been turned in 2. You must show your complete work . Points will be awarded only based on what appears in your answers. 3. If you prefer , you can type your answers using a word processor, rather than hand-writing them on this exam. 4. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures. Problem Type Points Score 1 Discussion Questions 20 2 Power Modeling 10 3 Modern Cache Coherence Protocols 15 4 Virtually-indexed Coherent Caches 15 5 Out-of-order Scheduling Replay 20 Total 80
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ECE/CS 752 Spring 2008 Midterm 2 -- Page 2 1. Discussion Questions [20 pts] a. [3 pts] Fine-grained multithreading, coarse-grained multithreading, and simultaneous multithreading are all used to interleave the execution of multiple threads on a single processor. Explain when and how instructions from multiple threads are introduced into and execute within the processor under each scheme. Not provided (in the book). b. [3 pts] Modern processors separate wakeup and select and data forwarding (or data capture) into separate pipeline stages to improve cycle time. In order to achieve high performance, this requires speculative scheduling. Explain why, and identify two challenging requirements that the recovery mechanism for a speculative scheduler must satisfy. Cycle time reasons. Predict all loads hit the cache (fixed latency). Must recover on cache misses. Recovery mechanism should be faster than wakeup propagation, otherwise it will never catchup. Also it must reach the transitive closure of dependent ops. c. [2 pts] In a multiscalar processor, what major functions did the sequencer perform? Not provided (in the paper).
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ECE/CS 752 Spring 2008 Midterm 2 -- Page 3 d. [2 pts] Describe the purpose and operation of the Multiscalar ARB. Not provided (in the paper). e. [3 pts] Compare and contrast the key differences between FPM, EDO, SDRAM, and RDRAM main memory technologies. Not provided (in the paper)
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ECE/CS 752 Spring 2008 Midterm 2 -- Page 4 f. [4 pts] Sequential consistency requires all memory references to appear to other processors in the system as if they were executed in original program order.
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at University of Wisconsin.

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exam2_s08_solution - Last (family) name: _ First (given)...

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