lect05-superscalar-org

lect05-superscalar-org - Superscalar Organization...

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Unformatted text preview: Superscalar Organization Superscalar Organization Prof. Mikko H. Lipasti University of Wisconsin-Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Limitations of Scalar Pipelines Limitations of Scalar Pipelines Scalar upper bound on throughput – IPC <= 1 or CPI >= 1 Inefficient unified pipeline – Long latency for each instruction Rigid pipeline stall policy – One stalled instruction stalls all newer instructions Parallel Pipelines Parallel Pipelines (a) No Parallelism (b) Temporal Parallelism (c) Spatial Parallelism (d) Parallel Pipeline Spatial Pipeline Unrolling Spatial Pipeline Unrolling Pipeline Unrolling - Power Pipeline Unrolling - Power 12-stage pipeline, 60% latch power, 25% latch delay+setup, 12% area on latches, 20% leakage power © Shen, Lipasti 5 Intel Pentium Parallel Pipeline Intel Pentium Parallel Pipeline IF D1 D2 EX WB IF IF D1 D1 D2 D2 EX EX WB WB U - Pipe V - Pipe Diversified Pipelines Diversified Pipelines • • • • • • • • • • • • IF ID RD WB ALU MEM1 FP1 BR MEM2 FP2 FP3 EX Power4 Diversified Pipelines Power4 Diversified Pipelines PC I-Cache BR Scan BR Predict Fetch Q Decode Reorder Buffer BR/CR Issue Q CR Unit BR Unit FX/LD 1 Issue Q FX1 Unit LD1 Unit FX/LD 2 Issue Q LD2 Unit FX2 Unit FP Issue Q FP1 Unit FP2 Unit StQ D-Cache Rigid Pipeline Stall Policy Rigid Pipeline Stall Policy Bypassing of Stalled Instruction Stalled Instruction Backward Propagation of Stalling Not Allowed Dynamic Pipelines Dynamic Pipelines • • • • • • • • • • • • IF ID RD WB ALU MEM1 FP1 BR MEM2 FP2 FP3 EX Dispatch Buffer Reorder Buffer ( in order ) ( out of order ) ( out of order ) ( in order ) Interstage Buffers Interstage Buffers...
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lect05-superscalar-org - Superscalar Organization...

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