lect07-instruction-flow

lect07-instruction-flow - InstructionFlowTechniques...

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ECE/CS 752:Advanced Computer Architecture I 1 Instruction Flow Techniques Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Instruction Flow Techniques Goal of Instruction Flow and Impediments Branch Types and Implementations What’s So Bad About Branches? What are Control Dependences? Impact of Control Dependences on Performance Improving I Cache Performance Instruction Flow in Context I-cache FETCH DECODE Branch Predictor Instruction Buffer Instruction Flow COMMIT D-cache Store Queue Reorder Buffer Integer Floating-point Media Memory Register Data Memory Data EXECUTE (ROB) Flow Flow Goal and Impediments Goal of Instruction Flow Supply processor with maximum number of useful instructions every clock cycle Impediment Impediments Branches and jumps Finite I Cache Capacity Bandwidth restrictions Branch Types and Implementation 1. Types of Branches A. Conditional or Unconditional B. Save PC? C. How is target computed? Single target (immediate, PC+immediate) Multiple targets (register) 2. Branch Architectures A. Condition code or condition registers B. Register Branch Types and Implementation 1. PowerPC CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 0 31 32 bit condition register–eight 4 bit fields (CR0 CR7) CR0 can be implicit result of integer op CR1 can be implicit result of FP op Compare ops set explicit CR field Special CR ops manipulate bits Conditional branch instructions test CR bits
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ECE/CS 752:Advanced Computer Architecture I 2 Branches–PowerPC 12 Types of Branches
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.

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lect07-instruction-flow - InstructionFlowTechniques...

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