lect09-adv-branch-prediction

lect09-adv-branch-prediction - AdvancedBranchPrediction

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ECE/CS 752:Advanced Computer Architecture I 1 Advanced Branch Prediction Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Advanced Branch Prediction Control Flow Speculation Branch Speculation Mis speculation Recovery Branch Direction Prediction Static Prediction Dynamic Prediction Hybrid Prediction Branch Target Prediction High bandwidth Fetch High Frequency Fetch Branch Speculation Leading Speculation Typically done during the Fetch stage Based on potential branch instruction(s) in the current fetch group Trailing Confirmation Typically done during the Branch Execute stage Based on the next Branch instruction to finish execution NT T NT T NT T T NT T NT T NT T (TAG 1) (TAG 2) (TAG 3) Branch Speculation Leading Speculation 1. Tag speculative instructions 2. Advance branch and following instructions 3. Buffer addresses of speculated branch instructions Trailing Confirmation 1. When branch resolves, remove/deallocate speculation tag 2. Permit completion of branch and following instructions Branch Speculation Start new correct path Must remember the alternate (non predicted) path Eliminate incorrect path Must ensure that the mis speculated instructions produce no side effects NT T NT T NT T NT T NT T T NT T (TAG 2) (TAG 3) (TAG 1) Mis speculation Recovery Start new correct path 1. Update PC with computed branch target (if predicted NT) 2. Update PC with sequential instruction address (if predicted T) 3. Can begin speculation again at next branch Eliminate incorrect path 1. Use tag(s) to deallocate ROB entries occupied by speculative instructions 2. Invalidate all instructions in the decode and dispatch buffers, as well as those in reservation stations
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ECE/CS 752:Advanced Computer Architecture I 2 Tracking Instructions Assign branch tags Allocated in circular order Instruction carries this tag throughout processor Track instruction groups Instructions managed in groups, max. one branch per group ROB structured as groups Leads to some inefficiency Simpler tracking of speculative instructions Program Control Flow Decode Buffer Fetch Dispatch Buffer Decode Reservation Dispatch Stations Issue Execute Finish Completion Branch to I-cache FA (fetch address) FA Branch Predictor Spec. target Prediction FA-mux SFX SFX CFX FPU LS BRN Buffer Branch Predictor Update Static Branch Prediction Single direction Always not taken: Intel i486 Backwards Taken/Forward Not Taken Loop closing branches Used as backup in Pentium Pro, II, III, 4 Heuristic based: void * p = malloc (numBytes); if (p == NULL) errorHandlingFunction( ); Static Branch Prediction Heuristic based: Ball/Larus Thomas Ball and James R. Larus. Branch Prediction for Free. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 300 313, May 1993.
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.

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lect09-adv-branch-prediction - AdvancedBranchPrediction

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