lect10-register-dataflow

lect10-register-dataflow - RegisterDataFlowTechniques...

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ECE/CS 752:Advanced Computer Architecture I 1 Register Data Flow Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Register Data Flow Techniques Register Data Flow Resolving Anti dependences Resolving Output Dependences Resolving True Data Dependences Tomasulo’s Algorithm [Tomasulo, 1967] Modified IBM 360/91 Floating point Unit Reservation Stations Common Data Bus Register Tags Operation of Dependency Mechanisms The Big Picture INSTRUCTION PROCESSING CONSTRAINTS Resource Contention Code Dependences Control Dependences Data Dependences True Dependences Anti-Dependences Output Dependences Storage Conflicts (Structural Dependences) (RAW) (WAR) (WAW) Register Data Flow Each ALU Instruction: Need Availability of F n (Structural Dependences) Need Availability of Rj, Rk (True Data Dependences) Need Availability of Ri (Anti-and output Dependences) INSTRUCTION EXECUTION MODEL Ri Fn (Rj, Rk) Dest. Reg. Funct. Unit Source Registers R0 R1 Rm FU 1 FU 2 FU n Interconnect Registers Functional Units “Register Transfer” “Read” “Write” “Execute” Causes of (Register) Storage Conflict REGISTER RECYCLING MAXIMIZE USE OF REGISTERS MULTIPLE ASSIGNMENTS OF VALUES TO REGISTERS OUT OF ORDER ISSUING AND COMPLETION LOSE IMPLIED PRECEDENCE OF SEQUENTIAL CODE LOSE 1-1 CORRESPONDENCE BETWEEN VALUES AND REGISTERS Ri Ri ••• DEF USE USE DEF ••• Ri Ri WAW WAR First instance of Ri Second instance of Ri Contribution to Register Recycling COMPILER REGISTER ALLOCATION INSTRUCTION LOOPS Single Assignment, Symbolic Reg. Map Symbolic Reg. to Physical Reg. Maximize Reuse of Reg. CODE GENERATION REG. ALLOCATION Reuse Same Set of Reg. in Each Iteration Overlapped Execution of Different Iterations For (k=1;k<= 10; k++) t += a [i] [k] * b [k] [j] ; 9 $34: mul $14 $7, 40 10 addu $15, $4, $14 11 mul $24, $9, 4 12 addu $25, $15, $24 13 lw $11, 0($25) 14 mul $12, $9, 40 15 addu $13, $5, $12 16 mul $14, $8, 4 17 addu $15, $13, $14 18 lw $24, 0($15) 19 mul $25, $11, $24 20 addu $10, $10, $25 21 addu $9, $9, 1 22 ble $9, 10, $34 “Spill code” (if not enough registers)
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ECE/CS 752:Advanced Computer Architecture I 2 Resolving Anti Dependences STALL DISPATCHING DELAY DISPATCHING OF (2) REQUIRE RECHECKING AND REACCESSING COPY OPERAND COPY NOT-YET-USED OPERAND TO PREVENT BEING OVERWRITTEN MUST USE TAG IF ACTUAL OPERAND NOT-YET-AVAILABLE RENAME REGISTER HARDWARE ALLOCATION (2) R3 R5 + 1 Must Prevent (2) from completing (1) R4 R3 + 1 before (1) is dispatched . R3 <= … <= R3 R3’ <= … <= R3’ WAR only and WAW © 2005 Mikko Lipasti 8 Resolving Output Dependences STALL DISPATCHING/ISSUING DENOTE OUTPUT DEPENDENCE HOLD DISPATCHING UNTIL RESOLUTION OF DEPENDENCE ALLOW DECODING OF SUBSEQUENT INSTRUCTIONS RENAME REGISTER HARDWARE ALLOCATION Must Prevent (3) from completing before (1) completes .
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.

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lect10-register-dataflow - RegisterDataFlowTechniques...

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