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Unformatted text preview: Memory Data Flow Prof. Mikko H. Lipasti University of WisconsinMadison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Memory Data Flow Memory Data Flow Memory Data Dependences Load Bypassing Load Forwarding Speculative Disambiguation The Memory Bottleneck Cache Hits and Cache Misses Memory Data Dependences Besides branches, long memory latencies are one of the biggest performance challenges today. To preserve sequential (inorder) state in the data caches and external memory (so that recovery from exceptions is possible) stores are performed in order . This takes care of antidependences and output dependences to memory locations. However, loads can be issued out of order with respect to stores if the outoforder loads check for data dependences with respect to previous, pending stores. WAW WAR RAW store X load X store X : : : store X store X load X Memory Data Dependences Memory Aliasing = Two memory references involving the same memory location (collision of two memory addresses). Memory Disambiguation = Determining whether two memory references will alias or not (whether there is a dependence or not). Memory Dependency Detection : Must compute effective addresses of both memory references Effective addresses can depend on runtime data and other instructions Comparison of addresses require much wider comparators Example code: (1) STORE V (2) ADD (3) LOAD W (4) LOAD X (5) LOAD V (6) ADD (7) STORE W RA W WA R Total Order of Loads and Stores Keep all loads and stores totally in order with respect to each other. However, loads and stores can execute out of order with respect to other types of instructions. Consequently, stores are held for all previous instructions, and loads are held for stores. I.e. stores performed at commit point Sufficient to prevent wrong branch path stores since all prior branches now resolved Illustration of Total Order Load v Load x Load w Store v data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Address Unit Store v Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load w Store v Load x data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load w Store v Load x Load v Store w Load/Store Reservation Station data data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x data data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load w Load v Store w data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load v Store w data Load x Load x Load x Load x Load x Load x Load x Load x Load x Load x Load v Store w data Store w data cache addr cache write data Store v released Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle7 Cycle 8 Load v Add Add Load w Store w Load x Cycle 1 Cycle 2 Decoder ISSUING LOADS AND STORES WITH TOTAL ORDERING Address Unit Address Unit Load w...
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.
 Spring '09
 PROFGURISOHI

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