lect13-pentium-pro

lect13-pentium-pro - PentiumProCaseStudy...

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ECE/CS 752:Advanced Computer Architecture I 1 Pentium Pro Case Study Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Pentium Pro Case Study Microarchitecture Order 3 Superscalar Out of Order execution Speculative execution In order completion Design Methodology Performance Analysis Retrospective Goals of P6 Microarchitecture IA-32 Compliant Performance (Frequency - IPC ) Validation Die Size Schedule Power P6–The Big Picture 0 1 2 3 4 Reservation Station (20) Dispatch Decode Fetch 2 Cycles 4 Cycles 2 Cycles BTB/ICU BAC/Rename Allocation 2 Cycles MOB DCU IEU1 AGU0 IEU0 Fadd Fmul Imul Div AGU1 ROB RRF JEU (40x157) 2 cyc Memory Hierarchy Main Memory PCI 64 bit Level 1 instruction and data caches 2 cycle access time Level 2 unified cache 6 cycle access time Separate level 2 cache and memory address/data bus ICache (8KB) DCache (8Kb) BIU L2 Cache (256Kb) CPU 16 bytes Instruction Fetch I n s t. Bu f Inst. Length Decoder Lt h ICache Stream Buffer L2 Cache (256Kb) ddress Next Addr Other Fetch Requests 16 bytes 16 b yt es + m ar k Mux (8Kb) Cache t. Ro t a or Length Inst. Marks P r e d i ct on Marks Instruction Victim TLB Physical Addr. FetchA . Logic Branch Target Buffer (512) Prediction To Decode Instruction Data uct io Da 2 cycle Branch Target
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ECE/CS 752:Advanced Computer Architecture I 2 Instruction Cache Unit Stream Buffer ICache (8 Kb) Bus Interface Unit Fetch Address Lower 12 bits Lower 12 bits Upper 20 bits Victim Cache Data Mux Instruction Tag Array ITLB Hit/Miss Instruction Data Branch Target Buffer Fetch Addr. Tag 4-bit BHR Br. Offset 4 - bit B H Rs pec. T a r get Add . Way 0 128 S ets Fetch Add ag Br .O ffs et 4-bit BHR spec. Target Addr. Way 1 Way 3 PHT 16 ent ie s / Tag Compare Return Stack Prediction Control Logic Prediction & Target Addr. Fetch Address Pattern History Table (PHT) is not speculatively updated A speculative Branch History Register (BHR) and prediction state is maintained Uses speculative prediction state if it exist for that branch Branch Prediction Algorithm 0010 1 Br. History 0000 0001 0010 0011 0100 0101 10 1 Pattern Table State Machine 0010 11 10 Branch Execution Br. Pred. Current prediction updates the speculative history prior to the next instance of the branch instruction Branch History Register (BHR) is updated during branch execution Branch recovery flushes front end and drains the execution core Branch mis prediction resets the speculative branch history state to match BHR 0101 Speculative History 0110 1110 1111 . . . 0101 Spec. Pred. Instruction Decode 1 Instruction Buffer 16 bytes Macro-Instruction Bytes from IFU Decoder 0 Decoder 1 Decoder 2 Branch To Next Address Calc.
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lect13-pentium-pro - PentiumProCaseStudy...

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