lect13-pentium-pro

lect13-pentium-pro - Pentium Pro Case Study Prof. Mikko H....

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Unformatted text preview: Pentium Pro Case Study Prof. Mikko H. Lipasti University of Wisconsin-Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Pentium Pro Case Study Microarchitecture Order-3 Superscalar Out-of-Order execution Speculative execution In-order completion Design Methodology Performance Analysis Retrospective Goals of P6 Microarchitecture IA-32 Compliant Performance (Frequency - IPC ) Validation Die Size Schedule Power P6 The Big Picture MOB DCU IEU1 AGU0 IEU0 Fadd Fmul Imul Div AGU1 1 2 3 4 Reservation Station (20) Dispatch Decode Fetch 2 Cycles 4 Cycles 2 Cycles BTB/ICU BAC/Rename Allocation 2 Cycles ROB RRF JEU (40x157) 2 cyc Memory Hierarchy Level 1 instruction and data caches - 2 cycle access time Level 2 unified cache - 6 cycle access time Separate level 2 cache and memory address/data bus ICache (8KB) DCache (8Kb) BIU L2 Cache (256Kb) Main Memory PCI CPU 64 bit 16 bytes Instruction Fetch Cache Inst. Buf Inst. Rotator Inst. Length Decoder Length Inst. Marks Prediction Marks Instruction Victim ICache Stream TLB Buffer Physical Addr. L2 Cache (256Kb) Fetch Address Next Addr. Logic Other Fetch Requests Branch Target Buffer (512) Prediction To Decode 16 bytes 16 bytes + marks Instruction Data Mux Instruction Data (8Kb) 2 cycle Branch Target Instruction Cache Unit Stream Buffer ICache (8 Kb) Victim Cache Bus Interface Unit Data Mux Instruction Tag Array ITLB Hit/Miss Instruction Data Fetch Address Lower 12 bits Lower 12 bits Upper 20 bits Branch Target Buffer Fetch Addr. Tag 4-bit BHR Br. Offset 4-bit BHR spec. Target Addr. Way 0 128 Sets Fetch Addr. Tag 4-bit BHR Br. Offset 4-bit BHR spec. Target Addr. Way 1 F etch Addr. Tag 4-bit BHR Br. Offset 4-bit BHR spec. Target Addr. Way 3 Tag Compare PHT 16 entries/set Return Stack Prediction Control Logic Prediction & Target Addr. Fetch Address Pattern History Table (PHT) is not speculatively updated A speculative Branch History Register (BHR) and prediction state is maintained Uses speculative prediction state if it exist for that branch Branch Prediction Algorithm Current prediction updates the speculative history prior to the next instance of the branch instruction Branch History Register (BHR) is updated during branch execution Branch recovery flushes front-end and drains the execution core Branch mis-prediction resets the speculative branch history state to match BHR 1 1 1 1 Speculative History Br. History 0000 0001 0010 0011 0100 0101 0110 1110 1111 1 1 . . . Pattern Table State Machine 0101 0010 11 10 Spec. Pred. Branch Execution Br. Pred. Instruction Decode - 1 Branch instruction detection Branch address calculation - Static prediction and branch always execution One branch decode per cycle (break on branch) Instruction Buffer 16 bytes Macro-Instruction Bytes from IFU Decoder Decoder 1 Decoder 2 Branch Address Calc....
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.

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lect13-pentium-pro - Pentium Pro Case Study Prof. Mikko H....

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