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Unformatted text preview: ECE/CS 752:Advanced Computer Architecture I 1 Advanced Memory Hierarchy Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen and Mark Hill Updated by Mikko Lipasti Readings Read on your own: Review: Shen & Lipasti Chapter 3 W. H. Wang, J. L. Baer, and H. M. Levy. Organization of a two level virtual real cache hierarchy, Proc. 16th ISCA, pp. 140 148, June 1989 (B6) Online PDF D. Kroft. Lockup Free Instruction Fetch/Prefetch Cache Organization, Proc. International Symposium on Computer Architecture , May 1981 (B6) . Online PDF N.P. Jouppi. Improving Direct Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990 (B6) . Online PDF Discuss in class: Review due 3/24/2010: Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger, "Phase Change Technology and the Future of Main Memory," IEEE Micro, vol. 30, no. 1, pp. 143 143, Jan./Feb. 2010 Read Sec. 1, skim Sec. 2, read Sec. 3: Bruce Jacob, The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It, Synthesis Lectures on Computer Architecture 2009 4:1, 1 77. 2 Advanced Memory Hierarchy Coherent Memory Interface Evaluation methods Better miss rate: skewed associative caches, victim caches Reducing miss costs through software restructuring Higher bandwidth: Lock up free caches, superscalar caches Beyond simple blocks Beyond simple blocks Two level caches Prefetching, software prefetching Main Memory, DRAM Virtual Memory, TLBs Interaction of caches, virtual memory Coherent Memory Interface Out-of-order processor core Load Q Store Q Critical word bypass Level 1 tag array Level 1 data array Storethrough Q WB buffer MSHR Snoop queue WB buffer Fill buffer Level 2 tag array Level 2 data array System address and response bus System data bus Coherent Memory Interface Load Queue Tracks inflight loads for aliasing, coherence Store Queue Defers stores until commit, tracks aliasing Storethrough Queue or Write Buffer or Store Buffer Defers stores, coalesces writes, must handle RAW MSHR Tracks outstanding misses, enables lockup free caches [Kroft ISCA 91] Snoop Queue Buffers, tracks incoming requests from coherent I/O, other processors Fill Buffer Works with MSHR to hold incoming partial lines Writeback Buffer Defers writeback of evicted line (demand miss handled first) Evaluation Methods Counters Counts hits and misses in hardware see [Clark, TOCS 1983] Intel VTune tool Accurate Realistic workloads system, user, everything Requires machine to exist Hard to vary cache parameters Experiments not deterministic ECE/CS 752:Advanced Computer Architecture I 2 Evaluation Methods Analytical...
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.
- Spring '09