lect14-advanced-memory-hierarchy

lect14-advanced-memory-hierarchy - Advanced Memory...

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Unformatted text preview: Advanced Memory Hierarchy Prof. Mikko H. Lipasti University of Wisconsin-Madison Lecture notes based on notes by John P. Shen and Mark Hill Updated by Mikko Lipasti Readings • Read on your own: – Review: Shen & Lipasti Chapter 3 – W.-H. Wang, J.-L. Baer, and H. M. Levy. Organization of a two-level virtual-real cache hierarchy, Proc. 16th ISCA, pp. 140-148, June 1989 (B6) Online PDF – D. Kroft. Lockup-Free Instruction Fetch/Prefetch Cache Organization, Proc. International Symposium on Computer Architecture , May 1981 (B6) . Online PDF – N.P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990 (B6) . Online PDF • Discuss in class: – Review due 3/24/2010: Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger, "Phase-Change Technology and the Future of Main Memory," IEEE Micro, vol. 30, no. 1, pp. 143-143, Jan./Feb. 2010 – Read Sec. 1, skim Sec. 2, read Sec. 3: Bruce Jacob, “The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It,” Synthesis Lectures on Computer Architecture 2009 4:1, 1-77. 2 Advanced Memory Hierarchy • Coherent Memory Interface • Evaluation methods • Better miss rate: skewed associative caches, victim caches • Reducing miss costs through software restructuring • Higher bandwidth: Lock-up free caches, superscalar caches • Beyond simple blocks • Two level caches • Prefetching, software prefetching • Main Memory, DRAM • Virtual Memory, TLBs • Interaction of caches, virtual memory Coherent Memory Interface Coherent Memory Interface • Load Queue – Tracks inflight loads for aliasing, coherence • Store Queue – Defers stores until commit, tracks aliasing • Storethrough Queue or Write Buffer or Store Buffer – Defers stores, coalesces writes, must handle RAW • MSHR – Tracks outstanding misses, enables lockup-free caches [Kroft ISCA 91] • Snoop Queue – Buffers, tracks incoming requests from coherent I/O, other processors • Fill Buffer – Works with MSHR to hold incoming partial lines • Writeback Buffer – Defers writeback of evicted line (demand miss handled first) Evaluation Methods - Counters • Counts hits and misses in hardware – see [Clark, TOCS 1983] – Intel VTune tool • Accurate • Realistic workloads - system, user, everything • Requires machine to exist • Hard to vary cache parameters • Experiments not deterministic Evaluation Methods - Analytical • Mathematical expressions – Insight - can vary parameters – Fast – Absolute accuracy suspect for models with few parameters – Hard to determine many parameter values – Not widely used today Evaluation: Trace-Driven Simulation program input data execute and trace discard output trace file run cache simulator input cache parameters compute effective access from miss ratio repeat as needed input t cache , t miss Evaluation: Trace-Driven Simulation...
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