lect15-adv-microarchitecture

lect15-adv-microarchitecture - Advanced instruction...

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Unformatted text preview: Advanced instruction scheduling Ilhyun Kim & Mikko H. Lipasti 1 Advanced Microarchitecture Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by Ilhyun Kim Updated by Mikko Lipasti Outline Instruction scheduling overview Scheduling atomicity Speculative scheduling Scheduling recovery Complexity effective instruction scheduling techniques Building large instruction windows Runahead, CFP, iCFP Scalable load/store handling Control Independence Readings Read on your own: Shen & Lipasti Chapter 10 on Advanced Register Data Flow skim I. Kim and M. Lipasti, Understanding Scheduling Replay Schemes, in Proceedings of the 10th International Symposium on High performance Computer Architecture (HPCA 10), February 2004. Srikanth Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, and Mike Upton, Continual Flow Pipelines, in Proceedings of ASPLOS 2004, October 2004. Ahmed S. Al Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham H. Akkary, Transparent Control Independence, in Proceedings of ISCA 34, 2007. To be discussed in class To be discussed in class: T. Shaw, M. Martin, A. Roth, NoSQ: Store Load Communication without a Store Queue, in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006. Pierre Salverda, Craig B. Zilles: Fundamental performance constraints in horizontal fusion of in order cores. HPCA 2008: 252 263. Andrew Hilton, Santosh Nagarakatte, Amir Roth, "iCFP: Tolerating All Level Cache Misses in In Order Processors," Proceedings of HPCA 2009. Loh, G. H., Xie, Y., and Black, B. 2007. Processor Design in 3D Die Stacking Technologies. IEEE Micro 27, 3 (May. 2007), 31 48. Register Dataflow Instruction scheduling A process of mapping a series of instructions into execution resources Decides when and where an instruction is executed Data dependence graph Mapped to two FUs 1 2 3 4 5 6 FU0 FU1 n n+1 n+2 n+3 1 2 3 5 4 6 Instruction scheduling A set of wakeup and select operations Wakeup Broadcasts the tags of parent instructions selected Dependent instruction gets matching tags, determines if source operands are ready Resolves true data dependences Select Picks instructions to issue among a pool of ready instructions Resolves resource conflicts Issue bandwidth Limited number of functional units / memory ports Advanced instruction scheduling Ilhyun Kim & Mikko H. Lipasti 2 Scheduling loop Basic wakeup and select operations = = = = OR OR tag W tag 1 grant 0 request 0 broadcast the tag of the selected inst readyL tagL readyR tagR = = = = OR OR readyL tagL readyR tagR ready - request request n grant n grant 1 request 1 selected issue to FU Select logic Wakeup logic scheduling loop Wakeup and Select FU0 FU1 n n+1 1 2 3 Select 1 Wakeup 2,3,4 Wakeup / select Select 2, 3...
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