lect16-multiple-threads

lect16-multiple-threads - Executing Multiple Threads Prof...

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Executing Multiple Threads Prof. Mikko H. Lipasti University of Wisconsin-Madison
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Readings Read on your own: G. S. Sohi, S. E. Breach and T.N. Vijaykumar. Multiscalar Processors, Proc. 22nd Annual International Symposium on Computer Architecture, June 1995. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996 (B5) To be discussed in class: Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29.
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Executing Multiple Threads Thread-level parallelism Synchronization Multiprocessors Explicit multithreading Implicit multithreading: Multiscalar Niagara case study
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Thread-level Parallelism Instruction-level parallelism Reaps performance by finding independent work in a single thread Thread-level parallelism Reaps performance by finding independent work across multiple threads Historically, requires explicitly parallel workloads Originate from mainframe time-sharing workloads Even then, CPU speed >> I/O speed Had to overlap I/O latency with “something else” for the CPU to do Hence, operating system would schedule other tasks/processes/threads that were “time-sharing” the CPU
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Thread-level Parallelism Reduces effectiveness of temporal and spatial locality
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Thread-level Parallelism Initially motivated by time-sharing of single CPU OS, applications written to be multithreaded Quickly led to adoption of multiple CPUs in a single system Enabled scalable product line from entry-level single-CPU systems to high-end multiple-CPU systems Same applications, OS, run seamlessly Adding CPUs increases throughput (performance) More recently: Multiple threads per processor core Coarse-grained multithreading (aka “switch-on-event”) Fine-grained multithreading • Simultaneous multithreading Multiple processor cores per die Chip multiprocessors (CMP) Chip multithreading (CMT)
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Thread-level Parallelism Parallelism limited by sharing Amdahl’s law: Access to shared state must be serialized • Serial portion limits parallel speedup Many important applications share (lots of) state Relational databases (transaction processing): GBs of shared state Even completely independent processes “share” virtualized hardware through O/S, hence must synchronize access Access to shared state/shared variables Must occur in a predictable, repeatable manner Otherwise, chaos results Architecture must provide primitives for serializing access to shared state
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Synchronization
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Some Synchronization Primitives Only one is necessary Others can be synthesized Primitive
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at University of Wisconsin.

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lect16-multiple-threads - Executing Multiple Threads Prof...

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