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Lee_Kim_slides_2009 - Optimizing Total Power of Many-core...

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Optimizing Total Power of Many-core Processors Considering Voltage Scaling Limit and Process Variations Department of Electrical and Computer Engineering University of Wisconsin - Madison Jungseob Lee and Nam Sung Kim October 9, 2009 Outline Introduction Supply Voltage and Power Scaling Supply Voltage Scaling of Many-Core Processors Power Scaling of Many-Core Processors Impacts of Within-Die(WID) Spatial Process Variations Global Clocking Frequency Island Clocking Conclusions Parallel Processing Improved throughput of computing systems w/ more cores Throughput is limited by power+thermal constraints w/ all cores running Challenges: How do we Determine # of cores for best performance-power efficiency? Exploit process variations for multicore processors? Multicore processors [1] Serial processing Parallel processing [1] Source: http://www.interactivesupercomputing.com/starpexpress/042007/3_Task_Parallel.html [2] Source: NVIDIA GPU which has many cores [2] Types of Process variations Process variations Within-Die (WID) Variations Die-to-Die (D2D) Variations Wafer Scale Courtesy: K. Bowman from Intel A Systematic V th variation map for a 16-core processor The corresponding Norm F max and P leak map C2C frequency and leakage power variations due to spatial correlated WID variations become considerable. Supply Voltage Scaling 1 Supply voltage scaling of many-core processors Throughput w/ certain # of cores at max V DD (thus F max ) = Throughput w/ more cores at lower V DD (thus F max ) Potential throughput increase by many cores and lower V DD can reduce power. # of cores 4 Operating freq V DD # of cores 8 Operating freq Lower V than V DD Supply Voltage Scaling 2 Supply voltage scaling of many-core processors M·T cycle (V DD ) = M·((1 F) + F/N)·T cycle (V) M Number of operations T cycle Cycle time of a processor at supply voltage V DD Nominal supply voltage of base core processor F Fraction of operations parallelizable w/o overhead N Relative number of cores l V Scaled supply voltage of N x more cores PTM 32nm HP PTM 32nm LP Require higher V DD due to high V th > 40 %
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Dynamic Power Analysis 1 Dynamic power scaling Dynamic power of a base many-core processor P dyn,base = C eff ·V 2 DD ·F max (V DD ) Dynamic power of N x more cores than the base processor P dyn,N = ((1 F) ·(1+(N 1) ·K) + F ·N) ·C eff ·V 2 ·F max (V) = k(F, K, N) ·f(V) ·(V/V DD ) 2 ·P dyn,base P dyn,N Dynamic power of N x more cores K Fraction of dynamic power of idle cores k(F,K,N) ((1 F) ·(1+(N
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