Lee_Kim_slides_2009

Lee_Kim_slides_2009 - Optimizing Total Power of Many-core...

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Click to edit Master subtitle style Department of Electrical and Computer Engineering University of Wisconsin - Madison Optimizing Total Power of Many-core Processors Considering Voltage Scaling Limit and Process Variations Jungseob Lee and Nam Sung Kim October 9, 2009
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Outline l Introduction l Supply Voltage and Power Scaling l Supply Voltage Scaling of Many-Core Processors l Power Scaling of Many-Core Processors l Impacts of Within-Die(WID) Spatial Process Variations l Global Clocking l Frequency−Island Clocking l Conclusions
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l Parallel Processing l Improved throughput of computing systems w/ more cores l Throughput is limited by power+thermal constraints w/ all cores running l Challenges: How do we l Determine # of cores for best performance-power efficiency? l Exploit process variations for multicore processors? Multicore processors [1] Serial processing Parallel processing [1] Source: http://www.interactivesupercomputing.com/starpexpress/042007/3_Task_Parallel.html [2] Source: NVIDIA GPU which has many cores [2]
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l Types of Process variations Process variations Within-Die (WID) Variations Die-to-Die (D2D) Variations Wafer Scale Courtesy: K. Bowman from Intel A Systematic Vth variation map for a 16-core processor The corresponding Norm Fmax and Pleak map C2C frequency and leakage power variations due to spatial correlated WID variations become considerable.
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Supply Voltage Scaling1 l Supply voltage scaling of many-core processors l Throughput w/ certain # of cores at max VDD (thus Fmax) = Throughput w/ more cores at lower VDD (thus Fmax) l Potential throughput increase by many cores and lower VDD can reduce power. Ø # of cores 4 Ø Operating freq VDD Ø # of cores 8 Ø Operating freq Lower V than VDD
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Supply Voltage Scaling2 l Supply voltage scaling of many-core processors l M∙Tcycle(VDD) = M∙((1−F) + F/N)∙Tcycle(V) M Number of operations Tcycle Cycle time of a processor at supply voltage VDD Nominal supply voltage of base core processor F Fraction of operations parallelizable w/o overhead N Relative number of cores V Scaled supply voltage of N x more cores PTM 32nm HP PTM 32nm LP Require higher VDD due to high Vth > 40 % ↓
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Dynamic Power Analysis1 l Dynamic power scaling l Dynamic power of a base many-core processor ¢ Pdyn,base = Ceff ∙V2DD ∙Fmax(VDD) l Dynamic power of N x more cores than the base processor ¢
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at University of Wisconsin.

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Lee_Kim_slides_2009 - Optimizing Total Power of Many-core...

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