midterm1-review - ComputerArchitecture...

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ECE/CS 552: Introduction To Computer Architecture 1 ECE/CS 752: Midterm 1 Review Prof. Mikko H. Lipasti University of Wisconsin Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti Computer Architecture Instruction Set Architecture (IBM 360) … the attributes of a [computing] system as seen by the programmer. I.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation Amdahl Blaaw & Brooks physical implementation. ‐‐ Amdahl, Blaaw, & Brooks, 1964 Machine Organization (microarchitecture) ALUS, Buses, Caches, Memories, etc. Machine Implementation (realization) Gates, cells, transistors, wires Iron Law Processor Performance = --------------- Time Program Instructions Cycles Time = X X Architecture --> Implementation --> Realization Compiler Designer Processor Designer Chip Designer Program Instruction Cycle (code size) (CPI) (cycle time) Ideal Pipelining Comb. Logic n Gate Delay Gate Delay L Gate Delay L L BW = ~(1/n) n -- 2 n -- 2 BW = ~(2/n) Bandwidth increases linearly with pipeline depth Latency increases by latch delays Gate Delay L Gate Delay L Gate Delay L n -- 3 n -- 3 n -- 3 BW = ~(3/n) Pipelining Idealisms Uniform subcomputations Can pipeline into stages with equal delay Balance pipeline stages Identical computations Can fill pipeline with identical work Unify instruction types (example later) Independent computations No relationships between work units Minimize pipeline stalls Are these practical? No, but can get close enough to get significant speedup Example (quicksort/MIPS) # for (; (j < high) && (array[j] < array[low]) ; ++j ); # $10 = j # $9 = high # $6 = array # $8 = low bge done, $10, $9 mul $15, $10, 4 addu $24, $6, $15 lw $25, 0($24) mul $13, $8, 4 addu $14, $6, $13 lw $15, 0($14) bge done, $25, $15 cont: addu $10, $10, 1 . . . done: addu $11, $11, -1
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ECE/CS 552: Introduction To Computer Architecture 2 Resolution of Pipeline Hazards Pipeline hazards Potential violations of program dependences Must ensure program dependences are not violated Hazard resolution Static: compiler/programmer guarantees correctness Dynamic: hardware performs checks at runtime Pipeline interlock Hardware mechanism for dynamic hazard resolution Must detect and enforce dependences at runtime Pipeline Hazards Necessary conditions: WAR: write stage earlier than read stage Is this possible in IF RD EX MEM WB ? WAW: write stage earlier than write stage Is this possible in IF RD EX MEM WB ? RAW: read stage earlier than write stage Is this possible in IF RD EX MEM WB? If conditions not met, no need to resolve Check for both register and memory Forwarding Paths (ALU instructions) IF ID i+1: i+2: i+3: RD R1 R1 R1 FORWARDING b ALU PATHS a i: R1 i: R1 i: R1 (i i+1) Forwarding via Path a i+1: i+1: i+2: (i i+2) Forwarding via Path b (i i+3) i writes R1 before i+3 reads R1 ALU MEM WB R1 R1 c Review Pipelining Overview Control Data hazards Stalls Forwarding or bypassing
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This note was uploaded on 03/02/2012 for the course ECE 752 taught by Professor Profgurisohi during the Spring '09 term at Wisconsin.

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midterm1-review - ComputerArchitecture...

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