143f2010-09 - N.CHEUNG EE143, Fall 2010 Homework Assignment...

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Unformatted text preview: N.CHEUNG EE143, Fall 2010 Homework Assignment # 9 (Due November 5, Fri , 9am) Reading Assignment 1)EE143 Lecture Notes on Process Integration 2) Jaeger, pp.221-228 on CMOS integration 3) REPRINT on Bspace : Sections of Maly , Atlas of IC Technology narrative description of CMOS process flows In this homework assignment, we will practice designing process flows based on planar technology. You have to describe the process flow and to draw cross-sections of the devices at key processing steps. Problem 1 Generic NMOS Process Flow Draw the cross-sections of the NMOS device along the lines (i) A-A and (ii) B-B after (a) The silicon nitride CVD deposition step (b) The field oxide growth step (c) RIE poly-Si gate step (d) RIE of intermediate oxide and thermal oxide step (e) Hydrogen annealing step. A A B B Problem 1 process flow description Substrate Boron doped (100)Si Resistivity= 20 -cm Thermal Oxidation ~100 pad oxide CVD Si 3 N 4 ~ 0.1 um Lithography Pattern Field Oxide Regions RIE removal of Nitride and pad oxide Channel Stop Implant: 3x10 12 B/cm 2 60keV Thermal Oxidation to grow 0.45um oxide Wet Etch Nitrdie and pad oxide Ion Implant for Threshold Voltage control 8x10 11 B/cm 2 35keV Thermal Oxidation To grow 250 gate oxide LPCVD Poly-Si ~ 0.35um Dope Poly-Si to n+ with Phosphorus Diffusion source Substrate Boron doped (100)Si Resistivity= 20 -cm Thermal Oxidation ~100 pad oxide CVD Si 3 N 4 ~ 0.1 um Lithography Pattern Field Oxide Regions RIE removal of Nitride and pad oxide Channel Stop Implant: 3x10 12 B/cm 2 60keV Thermal Oxidation to grow 0.45um oxide Wet Etch...
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This note was uploaded on 03/03/2012 for the course EECS 142 taught by Professor Ee142 during the Spring '04 term at University of California, Berkeley.

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143f2010-09 - N.CHEUNG EE143, Fall 2010 Homework Assignment...

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