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Unformatted text preview: 1 EE143 Fall 2010 Homework Assignment #10 (Due Nov 12, Fri 9am) Midterm Exam #2 will be on Nov 16 (Tue) 5:00-6:30pm, Moffitt 101. Closed book exam, 4 sheets of notes allowed. Topics of HW#6-HW#9 will be included. Reading Assignment 1) Jaeger, pp.212-221 2)Summary sheet of EE143 layout rules (attached) 3) Optional Reading in Bpsace : “Design Rule Basics” f rom Physical Design of CMOS IC Using L-Edit , J.P. Uyemura. This general reading provides bakground info on why different rules are needed. Problem 1 MOS Transistor – a warmup exercise Your textbook shows the schematic layout of a MOSFET (not drawn to scale) with two contact holes for the source/drain. Use our EE143 layout design rules to do a minimum geometry layout which can accommodate two contact holes for the source and the drain. Given: The transistor channel length L = 4 and channel width W =8 Read here before you start your homework : The layout schematics shown below are not to scale. The exact layout may depend on the constraints imposed by the design rules. You have to do all layouts with a scale of 0.2” to 1 . A graph paper with such a scale is attached is also posted on the web. You can photocopy/print more copies for your homework a scale is attached is also posted on the web....
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This note was uploaded on 03/03/2012 for the course EECS 142 taught by Professor Ee142 during the Spring '04 term at University of California, Berkeley.
- Spring '04