143f2010-m1-soln - 1 Fall 2010 UNIVERSITY OF CALIFORNIA...

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1 Fall 2010 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Midterm Exam #1 Family Name _______________________ First name_________________SID___________________ Signature_____________ Solutions _________________________________________________ Make sure the exam paper has 7 pages (including cover page) + 3 pages of data for reference Instructions: DO ALL WORK ON EXAM PAGES This is a 90-minute exam (2 sheets of HANDWRITTEN notes allowed) Grading: The reader can only assess what you put down on the exam paper, not what is inside your brain. Please be concise with your answers. For answers requiring explanation, adding sketches can be very effective. To obtain full credit, show correct units and algebraic sign. Numerical answers orders of magnitude off will receive no partial credit. Problem 1 (20 points)________________ Problem 2 (20 points)_______________ Problem 3 (20 points) ________________ Problem 4 (20 points) ________________ Problem 5 (20 points) ________________ TOTAL (100 points) __________________
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2 Problem 1 Simple Process Flow (20 points total) Figures below (taken from your Jaeger textbook and homework) show the top view and cross-section of a MOSFET along the line A-A’ . (a) (7 points) Sketch the cross-section of the device along the line B-B’. Label all important features of the cross-section. (b) (5 points) The process starts with a p-type Si wafer. List ALL thermal oxidation steps and their purpose in this process sequence. 1.Pad oxide – relief thermal stress between Si and silicon nitride during field oxidation 2. Field oxidation – form isolation between devices 3. Gate oxidation – gate dielectric for MOSFET. (c) (5 points) The process starts with a p-type Si wafer. List ALL ion implantation steps and their purpose in this process sequence. 1. Channel stop implant – raise threshold voltage under field oxide 2. Source/Drain implant – form MOSFET source and drain. [ Optional- threshold voltage tailoring of MOSFET ] (d) (3 points) In this process flow, which step has the highest thermal budget for dopant diffusion? Briefly state your reasoning. Field oxidation, high temperature and long time to grow ~ 0.5-1 um of oxide p (channel stop) CVD SiO2 p- substrate SiO2 (FOX) Al p (channel stop) n+ CVD SiO2 B B’ Cross Section along the line A-A’ A A’
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3 Problem2 Ion Implantation (20 points total) (a) (i) (5 points) 1000 keV boron was implanted into n-type Si (N B = 10 15 /cm 3 ) to a dose of 10 15 /cm 2 .
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