143s2006-final-soln - 1 Spring 2006 UNIVERSITY OF...

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Unformatted text preview: 1 Spring 2006 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Final Exam Family Name _______________________ First name______________________SID_______________ Signature_____________ Sample Solutions _______________ Instructions: DO ALL WORK ON EXAM PAGES Make sure your copy of the exam paper has 11 pages (including cover page) This is a 3-hr exam (12 sheets of handwritten notes allowed) Problem 1 (40 points)________________ Problem 2 (20 points)_______________ Problem 3 (40 points) ________________ Problem 4 (40 points) ________________ Problem 5 (35 points) ________________ Problem 6 (25 points) ________________ TOTAL (200 points) __________________ Information which may be useful s =1.036 10-12 F/cm for Si ox =3.45 10 -13 F/cm for SiO 2 q =1.6 10-19 coulombs Boltzmann constant k = 8.62 10-5 eV/K n i of Si= 1.45 10 10 cm-3 at 300K E g of Si = 1.12 eV at 300K Electron Affinity of Si =4.15 eV Electric potential =(E f-E i )/q n= n i exp(q /kT) x d = [ 2 s q ( i-V a ) ( 1 N a + 1 N d ) ] 1/2 MOS: V GB = MS +V ox +V Si V FB = MS- 1 C ox [ Q f + 0 x ox x ox (x) x ox dx ] MOSFET I-V (n-channel): I DS = n W L C ox [ (V G- V T ) V DS- V DS 2 /2 ] (below saturation) I Dsat = n W L C ox [(V G-V T ) 2 /2] (above saturation) Grading: Whenever possible, use sketches to support your explanation. Show correct units and algebraic sign for numerical answers. No partial credit for numerical answers orders of magnitude off. 2 Problem 1 Lab Questions (40 points total) (a) (10 points) In Cory 218, we only have the following processing equipment: Mask aligner Spinning, baking, and development setups for photoresist and spin-on glass Wet chemical bench for cleaning and wet etching Oxidation furnace Annealing furnace Al evaporator. Describe a process sequence using ONLY the available equipment in Cory 218 to fabricate the following DRAM structure, which is simply an Al-gate n-channel MOSFET connected to a capacitor Process Description Cross-section 1) Spin on phosphorus doped SOG.: n+ region patterning (Mask 1). Drive-in. 2) Strip SOG . Thermal oxidation to form field oxide. 3) Gate oxide patterning after field oxide growth (Mask 2). Grow thin gate oxide. 4) Contact opening (Mask 3) 5) Alunminum deposition.: Metal patterning (Mask 4) Field Oxide Al Gate p-type Si Gate oxide Al electrode for capacitor Al Field Oxide Al Gate p-type Si Gate oxide Al electrode for capacitor Al Al Gate oxide boundary n+ Si boundary Capacitor MOSFET Al Gate oxide boundary n+ Si boundary Capacitor MOSFET 3 Problem 1 Lab Questions continued (b) (8 points) Suppose the lab has an ion implanter, which step(s) in the process sequence will you change to improve the MOS device performance of the Ee143 chip? What improvement will you expect?...
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143s2006-final-soln - 1 Spring 2006 UNIVERSITY OF...

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