Lec_18 - Professor N Cheung, U.C. Berkeley Lecture 18 EE143...

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Unformatted text preview: Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 1 IC Process Integration Example IC Process Flows Simple resistor NMOS - Generic NMOS Process Flow CMOS - Generic CMOS Process Flow Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap Advance MOS Techniques Twin Well CMOS , Retrograde Wells , SOI CMOS Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 2 Self-aligned channel stop with Local Oxidation (LOCOS) Si 3 N 4 CVD pad oxide Si LOCOS Process Flow Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 3 B + channel stop implant Si thermal oxidation (high temperature) FOX Self-aligned channel stop p p B dose ~10 13 /cm 2 Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 4 If poly or metal lines lie on top of the Field Oxide (FOX), they will form a parasitic MOS structure.If these lines carrying a high voltage, they may create an inversion layer of free carriers at the Si substrate and shorts out neighboring devices. The relatively highly doped Si underneath (the channel stop) raises the threshold voltage of this parasitic MOS. If this threshold voltage value is higher than the highest circuit voltage, inversion will not occur. SiO 2 p-Si metal Comment: Field Oxide Channel Inversion Inversion Layer Device 1 Device 2 Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 5 Comments : Non self-aligned alternative: P.R. 1 SiO 2 P + P + Si P + P + SiO2 2 B + 3 Disadvantages 1 Two lithography steps 2 Channel stop doping not FOX aligned Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 6 Self-aligned Source and Drain n + n + poly-Si gate As + n + n + As + Off Alignment Perfect Alignment * The n+ S/D always follows gate Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 7 Comment: Non self-aligned Alternative . n + n + 2 . n + n + Solution: Use gate overlap to avoid offset error. . n + n + 1 Channel not linked to S/D Stray capacitance Disadvantages: Two lithography steps, excess gate overlap capacitance Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 8 Lightly Doped Drain (LDD) LDD (1E17-to 1E18/cm3) Professor N Cheung, U.C. Berkeley Lecture 18 EE143 F2010 9 Lightly Doped Source/Drain MOSFET (LDD)...
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Lec_18 - Professor N Cheung, U.C. Berkeley Lecture 18 EE143...

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