Lec_27 - EE143 F2010 Final Exam Review EE143 LAB Professor...

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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 1 EE143 LAB 1
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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 2 EE143 Equipment in Cory 218
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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 3 Si wafer Processing Steps Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Watch out for materials compatibility issues (e.g. temperature limit) Planarity is desirable for lithography, etching, and thin-film deposition Whenever possible, use self-aligned structures
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Professor N Cheung, U.C. Berkeley 4 0 200 400 600 800 1000 1200 1400 Resist Exposure Resist Spin-on Resist Bake Evaporation Deposition Sputtering Deposition CVD Ion Implantation Post Implantation Anneal Thermal Oxidation Dopant Diffusion Epi Process Temperature in C Resist Reflow Al-Si Eutectic (560C) Si Melting Point (1412C) Processing Temperature and Material Failure Temperature
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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 5 Self-Aligned Silicide Process (SALICIDE) using Ion Implantation and Metal-Si reaction n + n + TiSi 2 (metal) poly-gate *Process Flow: Show Process Description and Cross-sections
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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 6 A Generic CMOS Process P-well CMOS
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Professor N Cheung, U.C. Berkeley Final Exam Review EE143 F2010 7 Layout Design Rules •Understand the meaning of the boundaries •Use EE143 design rule values •Actual layout may look different from conceptual layout when
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This note was uploaded on 03/03/2012 for the course EECS 142 taught by Professor Ee142 during the Spring '04 term at University of California, Berkeley.

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Lec_27 - EE143 F2010 Final Exam Review EE143 LAB Professor...

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