Chapter 05a - MSP430 ISA

Chapter 05a - MSP430 ISA - Chapter 5 MSP430 ISA The...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Chapter 5 – MSP430 ISA The Instruction Set
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
BYU CS/ECEn 124 Chapter 05a - MSP430 ISA 2 Topics to Cover… MSP430 ISA Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Emulated Instructions
Background image of page 2
BYU CS/ECEn 124 Chapter 05a - MSP430 ISA 3 Where Are We? Problems Algorithms Language (Program) Machine (ISA) Architecture Micro-architecture Circuits Devices Programmable Computer Specific Manufacturer Specific The “Gap”
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
BYU CS/ECEn 124 Chapter 05a - MSP430 ISA 4 Problem Machine More concrete, machine-dependent; error prone, harder to write, read, debug, maintain Abstract, machine-independent; easier to write, read, debug, maintain Assembler 415E 0001 410F 532F 5F0E 4EE1 0000 415E 0001 531E 410F 532F 5F0E 415D 0001 410F 532F 5F0D 4EED 0000 415F 0001 531F 410E 532E 5F0E 41EE 0000 Machine language instructions Instruction = Many cycles Levels of Transformation Compiler MOV.B   0x0001(SP),R14 MOV.W   SP,R15 INCD.W  R15 ADD.W   R15,R14 MOV.B   @R14,0x0000(SP) MOV.B   0x0001(SP),R14 INC.W   R14 MOV.W   SP,R15 INCD.W  R15 ADD.W   R15,R14 MOV.B   0x0001(SP),R13 MOV.W   SP,R15 INCD.W  R15 ADD.W   R15,R13 MOV.B   @R14,0x0000(R13) MOV.B   0x0001(SP),R15 INC.W   R15 MOV.W   SP,R14 INCD.W  R14 ADD.W   R15,R14 MOV.B   @SP,0x0000(R14) Assembly language instructions One statement = Many instructions Coder lampDoesntWork() { if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); } } High-level language statements One algorithm = Many statements Algorithm Problem solved by Algorithm Engineer Problem Problem
Background image of page 4
BYU CS/ECEn 124 Chapter 05a - MSP430 ISA 5 Instruction Set Architecture The computer ISA defines all of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). MSP430 ISA
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
BYU CS/ECEn 124 Chapter 05a - MSP430 ISA 6 MSP430 Instruction Set Architecture Implements RISC architecture with 27 instructions and 7 addressing modes. Orthogonal architecture with every instruction usable with
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/02/2012 for the course C S 124 taught by Professor Staff during the Fall '08 term at BYU.

Page1 / 20

Chapter 05a - MSP430 ISA - Chapter 5 MSP430 ISA The...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online