Chapter 06 - MSP430 Microarchitecture

Chapter 06 - MSP430 Microarchitecture - Chapter 6 MSP430...

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Chapter 6 – MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 2 Topics to Cover… MSP430 Microarchitecture Instruction Cycle Review Fetch Cycle Source Addressing Modes Evaluate Source Operand Destination Addressing Modes Evaluate Destination Operand Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 3 Levels of Transformation Problems Algorithms Language (Program) Machine Architecture (ISA) Microarchitecture Circuits Devices Programmable Computer Specific Manufacturer Specific
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 4 Microarchitecture Journey Transistor a b NOR Complementary Logic W X Y Z A B A B S C Combinational Logic Register Register Register Register we we we we we d q a 1 a 0 2-to-4 Decoder 4-to 1 Multiplexor Storage Devices Sequential Logic q q d we MSP430 Microarchitecture Finite State Machine ISA Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 5 Microarchitecture The Instruction Set Architecture (ISA) defines the processor instruction set, processor registers, address and data formats The processor as seen by an assembly language programmer. The microarchitecture implements the ISA. Gates, registers, ALUs Data and control paths Microarchitectures differentiate themselves by: Chip area/cost Power consumption Logic complexity Manufacturability Ease of debugging Testability MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 6 MSP430 ALU ALU (Arithmetic and Logic Unit) performs the arithmetic and logical operations Arithmetic operations: add, subtract, compare Logical operations: and, xor, bit Sets condition codes The word length of a computer is the number of bits processed by the ALU. MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 7 MSP430 Registers 16, 16-bit registers R0 = Program Counter R1 = Stack Pointer R2 = Status Register R3 = Constant Generator R4 – R15 = General Purpose Registers Very fast memory - close to the ALU ( register file ). MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 8 MSP430 Control Unit The control unit directs the execution of the program The program counter or PC points to the next instruction to be executed The instruction register or IR contains the currently executing instruction The status register or SR contains information about the last instruction executed as well as system parameters The control unit prevents bus conflicts and timing/propagation problems The control unit is a Finite State Machine driven by a clock MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 9 MSP430 Clock MSP430 Microarchitecture
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BYU CS/ECEn Chapter 6 - MSP430 Microarchitecture 10 MSP430 Memory Interrupt vectors - Upper 16 words of Flash Flash / ROM - Used for both code and data
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This note was uploaded on 03/02/2012 for the course C S 124 taught by Professor Staff during the Fall '08 term at BYU.

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Chapter 06 - MSP430 Microarchitecture - Chapter 6 MSP430...

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