Lecture 4

Lecture 4 - 2/8/2012 CNIT 17600 Lecture 4 CPU Architectures...

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2/8/2012 1 CPU Architectures and Instruction Sets CNIT 17600 – Lecture 4 Instruction Formats Instruction sets are differentiated by the following: Number of bits per instruction Stack-based or register-based Number of explicit operands per instruction Operand location Types of operations Type and size of operands
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2/8/2012 2 Instructions Instruction Lowest-level command A bit string, logically divided into components operation code(s) and operand(s) Structure Op code position and length Operand position, type, and length Vary among architectures op code size, meaning of specific op code values, data types used as operands, length and coding format of each type of operand 3 Op Code and Operands Op Code Unique binary number for an instruction Operands Input values for the instruction 4
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2/8/2012 3 Instruction Formats Instruction set architectures are measured according to: Main memory space occupied by a program Instruction complexity Instruction length (in bits) Total number of instructions in the instruction set Instruction Formats In designing an instruction set, consideration is given to: Instruction length Whether short, long, or variable Number of operands Number of addressable registers Memory organization Whether byte- or word addressable Addressing modes Direct, indirect or indexed
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2/8/2012 4 Endianness Byte ordering, or endianness , is another major architectural consideration If we have a two-byte integer, the integer may be stored so that the least significant byte is followed by the most significant byte or vice versa In little endian machines, the least significant byte is followed by the most significant byte Big endian machines store the most significant byte first (at the lower address) 7 Endianness As an example, suppose we have the number 0x12345678 8
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2/8/2012 5 Endianness Big endian: Is more natural for human readability The sign of the number can be determined by looking at the byte at address offset 0 Strings and integers are stored in the same order Little endian: Makes it easier to place values on non-word boundaries Conversion from a 16-bit integer address to a 32-bit integer address does not require any arithmetic 9 CPU Data Storage Format The next consideration for architecture design concerns how the CPU stores data Three choices: Stack architecture Accumulator architecture General purpose register architecture In choosing one over the other, the tradeoffs are simplicity (and cost) of hardware design with execution speed and ease of use 10
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2/8/2012 6 Stack Architecture instructions and operands are implicitly taken from the stack A stack cannot be accessed randomly Instruction Formats Stack machines use one- and zero-operand instructions LOAD and STORE instructions require a single memory address operand Other instructions use operands from the stack implicitly PUSH and POP operations involve only the stack’s top element Binary instructions (e.g., ADD , MULT ) use the top two items on the stack 12
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2/8/2012 7 Instruction Formats
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This note was uploaded on 03/04/2012 for the course CNIT 176 taught by Professor Hansen during the Spring '09 term at Purdue.

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Lecture 4 - 2/8/2012 CNIT 17600 Lecture 4 CPU Architectures...

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