Lecture_19 - Chapter 5 Large and Fast: Exploiting Memory...

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 2 Memory Protection Different tasks can share parts of their virtual address spaces But need to protect against errant access Requires OS assistance Hardware support for OS protection Privileged supervisor mode (aka kernel mode) Privileged instructions Page tables and other state information only accessible in supervisor mode System call exception (e.g., syscall in MIPS)
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 3 The Memory Hierarchy Common principles apply at all levels of the memory hierarchy Based on notions of caching At each level in the hierarchy Block placement Finding a block Replacement on a miss Write policy §5.5 A Common Framework for Memory Hierarchies The BIG Picture
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 4 Block Placement Determined by associativity Direct mapped (1-way associative) One choice for placement n-way set associative n choices within a set Fully associative Any location Higher associativity reduces miss rate Increases complexity, cost, and access time
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 5 Finding a Block Hardware caches Reduce comparisons to reduce cost Virtual memory Full table lookup makes full associativity feasible Benefit in reduced miss rate Associativity Location method Tag comparisons Direct mapped Index 1 n-way set associative Set index, then search entries within the set n Fully associative Search all entries #entries Full lookup table 0
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 6 Replacement Choice of entry to replace on a miss Least recently used (LRU) Complex and costly hardware for high associativity Random Close to LRU, easier to implement Virtual memory LRU approximation with hardware support
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 7 Write Policy Write-through Update both upper and lower levels Simplifies replacement, but may require write buffer Write-back Update upper level only Update lower level when block is replaced Need to keep more state Virtual memory Only write-back is feasible, given disk write latency
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 8 Sources of Misses Compulsory misses (aka cold start misses) First access to a block Capacity misses Due to finite cache size A replaced block is later accessed again Conflict misses (aka collision misses) In a non-fully associative cache Due to competition for entries in a set Would not occur in a fully associative cache of the same total size
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Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 9 Cache Design Trade-offs Design change Effect on miss rate Negative performance effect Increase cache size
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Lecture_19 - Chapter 5 Large and Fast: Exploiting Memory...

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