Lecture_15 - Chapter 4 The Processor Stalls and Performance The BIG Picture Stalls reduce performance But are required to get correct results

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Chapter 4 The Processor
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Chapter 4 — The Processor — 2 Stalls and Performance Stalls reduce performance But are required to get correct results Compiler can arrange code to avoid hazards and stalls Requires knowledge of the pipeline structure The BIG Picture
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Chapter 4 — The Processor — 3 Branch Hazards If branch outcome determined in MEM §4.8 Control Hazards PC Flush these instructions (Set control values to 0)
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Chapter 4 — The Processor — 4 Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7 ... 72: lw $4, 50($7)
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Chapter 4 — The Processor — 5 Example: Branch Taken
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Chapter 4 — The Processor — 6 Example: Branch Taken
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Chapter 4 — The Processor — 7 Data Hazards for Branches If a comparison register is a destination of 2 nd or 3 rd preceding ALU instruction IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB add $4 , $5, $6 add $1 , $2, $3 beq $1 , $4 , target Can resolve using forwarding
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Chapter 4 — The Processor — 8 Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2 nd preceding load instruction Need 1 stall cycle beq stalled IF ID EX MEM WB IF ID EX MEM WB IF ID ID EX MEM WB add $4 , $5, $6 lw $1 , addr beq $1 , $4 , target
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Chapter 4 — The Processor — 9 Data Hazards for Branches If a comparison register is a destination of
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This note was uploaded on 03/07/2012 for the course CS 2506 taught by Professor Srinidhivaradarajan during the Spring '12 term at Virginia Tech.

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Lecture_15 - Chapter 4 The Processor Stalls and Performance The BIG Picture Stalls reduce performance But are required to get correct results

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