Lecture_13 - Chapter 4 The Processor Chapter 4 The...

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Unformatted text preview: Chapter 4 The Processor Chapter 4 The Processor 2 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pipelining Chapter 4 The Processor 3 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance 4.5 An Overview of Pipelining Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup = 2n/0.5n + 1.5 4 = number of stages Chapter 4 The Processor 4 MIPS Pipeline Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register Chapter 4 The Processor 5 Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register read ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps Chapter 4 The Processor 6 Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) Chapter 4 The Processor 7 Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructions pipelined = Time between instructions nonpipelined Number of stages...
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This note was uploaded on 03/07/2012 for the course CS 2506 taught by Professor Srinidhivaradarajan during the Spring '12 term at Virginia Tech.

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Lecture_13 - Chapter 4 The Processor Chapter 4 The...

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