10 - Scheduling What makes instruction scheduling hard?...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Scheduling Previously Value Numbering Today : Scheduling to Minimize Register pressure Introduction to scheduling Scheduling a basic block Sethi-Ullman Numbering (quick review) Proebsting & Fischer CS 380C Lecture 10 1 Scheduling What makes instruction scheduling hard? Instruction data path IF Reg ALU DM Reg2 IF : Instruction Fetch Reg : Instruction Decode/Register Fetch ALU :Execute/Fetch DM : Memory Access Reg2 :W r i teBack Pipelining Instead of: Instr Instr Instr Instr We do: Instr Instr Instr Instr By instruction component and cycle: 12 3 4 5 6 7 8 9 IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg CS 380C Lecture 10 2 Scheduling
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Pipelining 12 3 4 5 6 7 8 9 IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg IF Reg ALU DM Reg Potential speed up = number of stages in the pipeline time to drain and ±ll pipeline limits speed up Rate through the pipeline is limited by the slowest stage No individual instruction executes any faster Modern Processors (aside) Multi-issue: 2, 4, or more instructions issued per cycle Dynamic run-time scheduling of some window (16-64) of instructions Speculate branches, loads, values . .. CS 380C Lecture 10 3 Scheduling What makes scheduling a pipeline hard? Structural hazards: when the hardware cannot support all possible combinations of instructions in the pipeline because of resource con²icts Data hazards: an instruction depends on the result of a previous instruction which is still in the pipeline. Control hazards: arise due to branches and any other instruction that modi±es the PC and a³ects which instructions should be in the pipeline. One solution = Insert bubbles CS 380C Lecture 10 4 Scheduling
Background image of page 2
Bubbles Control Hazard : worst case: (btru R1, R2; inst2) 12 3 4 567 8 91 0 IF Reg ALU DM Reg ±±± ± IF Reg ALU DM Reg Structural Hazard 3cyc lemu lt ip ly :(mu lt1 , r1 , r2 ;mu lt2 , r3 , r4) 123 4 5 6 7 8 0 IF Reg ±± ALU DM Reg IF Reg ALU DM Reg IF ... or 34 5 6 7 8 0 IF Reg ALU DM Reg IF Reg ± ± ALU DM Reg IF CS 380C Lecture 10 5 Scheduling Other solutions Structural hazards: hardware functional unit replication compiler instruction scheduling Data hazards: partial solution - hardware forwarding compiler instruction scheduling sensitive to accuracy of aliasing runtime speculation Control hazards: runtime speculation compiler instruction scheduling Is there a pattern here? CS 380C Lecture 10 6 Scheduling
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Scheduling for a Pipelined Architecture SimpliFcation: consider only data (register and memory) hazards ( a.k.a., interlocks). Goal: an efcient, compile-time algorithm For reordering instructions to minimize the number oF stalls (bubbles) in the pipeline. This scheduling is perFormed aFter code generation and register allocation.
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 13

10 - Scheduling What makes instruction scheduling hard?...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online