25-1 - Compiling for EDGE Architectures: The TRIPS...

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ASPLOS XII March 9, 2012 Compiling for EDGE Architectures: The TRIPS Prototype Compiler Kathryn McKinley Doug Burger, Steve Keckler,  Jim Burrill 1 , Xia Chen, Katie Coons, Sundeep Kushwaha, Bert Maher, Nick  Nethercote, Aaron Smith, Bill Yoder et al. The University of Texas at Austin 1 University of Massachusetts, Amherst
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ASPLOS XII March 9, 2012 130 nm 100 nm 70 nm 35 nm 20 mm chip edge Analytically … Qualitatively … Either way … Partitioning for on-chip communication is key Technology Scaling Hitting the Wall
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ASPLOS XII March 9, 2012 Clock ride is over Wire and pipeline limits Quadratic out-of-order issue logic Power, a first order constraint Problems for any architectural solution ILP - instruction level parallelism Memory and on-chip latency Major vendors ending processor lines OO SuperScalars Out of Steam
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ASPLOS XII March 9, 2012 Clock ride is over Wire and pipeline limits Quadratic out-of-order issue logic Power, a first order constraint Problems for any architectural solution ILP - instruction level parallelism Memory and on-chip latency Major vendors ending processor lines OO SuperScalars Out of Steam What’s next?  
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ASPLOS XII March 9, 2012 Post-RISC Solutions CMP - An evolutionary path Replicate what we already have 2 to N times on a chip Coarse grain parallelism Exposes the resources to the programmer and compiler Explicit Data Graph Execution (EDGE) 1. Program graph is broken into sequence of blocks Blocks commit atomically or not - a block never partially commits 2. Dataflow within a block, ISA support for direct producer-consumer communication No shared named registers (point-to-point dataflow edges only) Memory is still a shared namespace The block’s dataflow graph (DFG) is explicit in the architecture
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ASPLOS XII March 9, 2012 Outline TRIPS Execution Model & ISA TRIPS Architectural Constraints Compiler Structure Spatial Path Scheduling
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ASPLOS XII March 9, 2012 Block Atomic Execution Model ld shl sw br add add ld cmp shl ld cmp br TRIPS block - single entry constrained hyperblock Dataflow execution w/ target position encoding write write read read read sw sw add br write Dataflow Graph TRIPS block Flow Graph Execution Substrate read Register File Data Caches D[0] Gtile write read write bro_t addi addi lw_f mov addi read lw_f Gtile D[0] addi write bro_t addi mov addi write
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ASPLOS XII March 9, 2012 TRIPS Block Constraints Fixed Size : 128 instructions Padded with no-ops if needed Load/Store Identifiers: 32 load or store queue identifiers More than 32 static loads and stores is possible Registers : 32 reads and 32 writes, 8 to each of 4 banks (in addition to 128) 1 - 128 instruction DFG Register banks Memory PC PC 32 reads 32 writes 32 loads 32  stores PC read terminating branch Constant Output : all stores and writes execute, one branch Simplifies hardware logic for detecting block completion
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25-1 - Compiling for EDGE Architectures: The TRIPS...

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